| Mfg | pack | D/C | Descrpion | ||
| V.3 | (3) | AT&T | PLCC68 | 9525+ | Packets received from the packet interfaces are parsed to determine the eg |
| V/3 | (1) | ||||
| V-0 | (9) | AMI | 08+ | The temperature of the lead should be measured using a ther- mocouple pl | |
| V0- | (1) | N/A | PLCC-44 | 00 | The ADG884 is a low voltage CMOS device containing two independently sel |
| V00 | (9) | 97 | Sector Write The sector write mode requires issuing the 8-bit write com | ||
| V01 | (11) | YAMAHA | MQFP2828 | 02+ | MX7575KN0C to +70C18 Plastic DIP MX7575JCWN0C to +70C18 Wi |
| V02 | (1) | ERICSSON | DIP | This method fails if a user applies RESET during the FPGA configuration | |
| V03 | (7) | TOS | BGA | BGA | FEATURES lPhototransistor output lOpaque housing provides improved &nbs |
| V04 | (5) | N/A | Logic supply Logic input for high side gate driver output (HO), in phase | ||
| V05 | (5) | HP | 05+/06+ | The 78P7200 is a single chip line interface IC designed to work with eith | |
| V06 | (10) | N/A | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | ||
| V07 | (19) | H | 01+ | PLCC-28 | The V076133261 allows designers a great deal of flexibility in selecting |
| V08 | (7) | FUJITSU | SMD | 2005 | A typical interface circuit using the SPT1018 in a color raster applicat |
| V09 | (9) | ST | SSOP | The entire series has Underwriters Laboratory Recognition for the | |
| V0H | (1) | The bq2014 measures the voltage differential between the SR and VSS pins. | |||
| V0S | (1) | † All characteristics are measured under open-loop conditions, with | |||
| V-1 | (23) | N/A | 01+ | This protection function is splitted in 2 stages. As shown in Figure A3, | |
| V1- | (20) | SIEMENS | PQFQ | 2000 | * This is a stress rating only and functional operation of the device at |
| V1. | (9) | 00 | The low-cost ADS-944 is a high-performance, 14-bit, 5MHz sampling A/D c | ||
| V10 | (128) | VTC | PLCC28 | 03/+04+ | A series output switch eliminates the need for external multiplexing in |
| V11 | (21) | ALPHA | SOP-6 | Chapter 4, "Control Registers," contains overview tables for all | |
| V12 | (52) | ＬＩＴＴＥＬＦＵＳＥ | Information at the D inputis transferred to the Q outputs on the positiv | ||
| V13 | (47) | HARRIS | 97 | HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC | |
| V14 | (44) | har | har | dc00 | |
| V15 | (64) | H | 01+ | PLCC-28 | |
| V16 | (21) | JPN | 2000 | 05+ | The MSK 5115-00 is an adjustable version in the series of high performan |
| V17 | (19) | 08+ | |||
| V18 | (62) | LG | SOP | 2002 | In most applications the input coupling capacitors are 0.1µF. The |
| V19 | (19) | V | TSSOP | 06+ | Digital processing at 1fH level ITU 656 decoder Double window and pict |
| V1F | (1) | The MAX8758 includes a high-performance step-up regu- lator, a high-speed | |||
| V1G | (1) | TOSHIBA | The program operation is initiated by a 4-byte command cycle (see Command | ||
| V1P | (1) | ST8 | 07+ | TAOperating free-air temperature−40125C NOTE 4: All unused c | |
| V1Z | (1) | 5. The ALD1704 operational amplifier has been designed to provide full & | |||
| V-2 | (2) | N/A | OMRON | 05+ | DC Supply voltage pin 2 1) Output current Power Good and Fault Collect |
| V2. | (5) | ||||
| V20 | (55) | har | har | dc98 | The UC382 allows for Kelvin sensing the voltage at the load. This improve |
| V21 | (17) | NAIS | DIP6 | Programmable options include the length of pipeline (Read latency of 2 or | |
| V22 | (54) | REND | BGA | 98+ | 150V Power Schottky rectifier are suited for switch Mode Power Supplies |
| V23 | (601) | sie | sie | dc98 | The switching safe operating area (SOA) of Figure 9 is the bounda |
| V24 | (437) | N/A | • Control and safety devices for airplanes, trains, automobiles, and | ||
| V25 | (44) | HAR | 905 | n CAN I/F CAN serial bus interface block as described in the CAN | |
| V26 | (24) | AGILENT | DIP | Radiation Hardened up to 1 x 106 Rads (Si) Single Event Burnout (SEB) H | |
| V27 | (71) | littelfuse | littelfuse | dc0310 | The pulse width is controlled by means of an external po- tentiometer (4 |
| V28 | (9) | INFINEON | QFP | These counters are fully programmable; that is, they can be preset to any | |
| V29 | (36) | . | . | 3 | Note 2: The algebraic convention is used in this data sheet; the most nega |
| V2B | (1) | 500 | 97+ | Switching behavior is most easily modeled and predicted by recogn | |
| V2F | (9) | ★Original and new, Special price! | DIP | 06+ | The XC62K series are highly precise, low power consumption, negative vol |
| V2M | (1) | The GC1012A chip used a slow internal clock to power down the chip | |||
| V3 | (1) | CAUTION: These devices are sensitive to electrostatic discharge; f | |||
| V-3 | (1) | Ｓiemens | PLCC-44 | 06+ | High density internet E1 or T1 / J1 interface for routers, multiplex- er |
| V3- | (11) | HARRIS | 00+ | DIP-8 | The attached datasheets are prepared and approved by SAMSUNG Electr |
| V3. | (15) | NSC | 2008 | 1.1 Scope. This specification covers the performance requirements | |
| V30 | (631) | N/A | N/A | N/A | Stresses above these ratings may cause permanent damage. Exposure to ab |
| V31 | (6) | INFINEON | 00+ | SOP | 2. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 3. VIL (mi |
| V32 | (77) | LUCENT | PLCC84 | 03/+04+ | When the PHY-LLC interface is in the low-power disabled state, the TSB41A |
| V33 | (31) | AD | SOT23 | 6+ | Input voltage. For regulation at full load, the input to this pin must be |
| V34 | (9) | TI | SMD | Note 7: The average voltage that the weakest pin combinations (those invo | |
| V35 | (9) | SMD-8 | 04/05+ | Note 1: For the force-sense versions, FB_ is connected to its respective O | |
| V36 | (16) | 00+ | QFP/160 | Host clock frequency selection is achieved by applying the appropriate lo | |
| V37 | (355) | VICOR | Conforms to JEDEC byte-wide standard Reliable CMOS with MNO | ||
| V38 | (20) | 2 | BGA | g This device fully meets the reliability and quality control stand | |
| V39 | (81) | This demonstrates that with more complex devices the con- cept of CPD gr | |||
| V3B | (1) | Note : The curves of the figure 3 are specified for a junction temperatur | |||
| V3F | (1) | AV | 10000 | 32K x 8-bit organization. Very high speed 12,15,20 ns. | |
| V3L | (1) | The floating-point control register space contains two registers: | |||
| V3M | (1) | T | PLCC84 | 03/+04+ | Each DS1265 device is shipped from Dallas Semiconductor with its lithium |
| V3N | (1) | sgs | sgs | dc93 | The LP2950 and LP2951 are micropower voltage regulators with very low q |
| V-4 | (2) | HARRIS | DIP-8 | 00+ | 16 E1, T1, or J1 Short-Haul Line Interface Units Independent E1, T1, or J |
| V4. | (1) | PHI | QFP-44 | 00 | CAUTION: Stresses above those listed in Absolute Maximum Ratings may caus |
| V40 | (41) | Mikroelektronik Erfurt | WD | COMMAND (Digital-to-Analog Converter Output Voltage): This pin is the out | |
| V41 | (2) | COSMO | 06+ | 2400 | Note 1: Absolute maximum ratings indicate limits beyond which damage to t |
| V42 | (142) | ge | n/a | Threshold Current (BOL) Wavelength Wavelength Tuning Coefficient Exte | |
| V43 | (15) | ＬＩＴＴＥＬＦＵＳＥ | CAUTION: These devices are sensitive to electrostatic discharge; f | ||
| V44 | (3) | The DP8402 check bit syndrome matrix can be seen in TA- BLE II The horiz | |||
| V45 | (7) | TOSHIBA | DIP-30 | 92+ | Acknowledge Each receiving device, when addressed, is obliged to generate |
| V47 | (26) | ＬＩＴＴＥＬＦＵＳＥ | • Selectable 150 Ω and 100 Ω termination for shielded or | ||
| V48 | (486) | 55 | MODULE | ANT1/ANT2 High Output Power (7.5 dBm) with Low Supply Current (9.0 mA) M | |
| V49 | (3) | SOJ | 95 | READ: The AT28C010-12DK is accessed like a Static RAM. When CE and OE are | |
| V4B | (1) | Just as the USB Interrupt is shared among 27 individual USB- interrupt | |||
| V4D | (1) | MOSEL | The ULN2001A, ULN2002A, ULN2003 and ULN2004Aare high voltage, high curr | ||
| V4N | (2) | Device programming occurs by executing the program command sequence. This | |||
| V4T | (1) | 82 | QFP | NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle r | |
| V-5 | (1) | 99 | † A-to-B data flow is shown. B-to-A data flow is similar, but uses | ||
| V5- | (3) | OMRON | s Up to 47 5 V tolerant general purpose I/O pins in tiny LQFP64 package. | ||
| V5. | (21) | JET | DIP | Operating voltage VCC: 2.4~5.5V Low power consumption C Operating: 5mA m | |
| V5/ | (1) | 2. When using this product, please observe the absolute maximum ratings an | |||
| V50 | (45) | SMD | 9830 | The architecture of the devices consists of a series of programmable I/ | |
| V51 | (21) | har | har | dc00 | The TO-220 Fullpak eliminates the need for additional insulating hardware |
| V52 | (21) | MITSUBISHI | SOP | 00+ | Texas Instruments reserves the right to change its products and services |
| V53 | (303) | 1.1 EMI REDUCTION The COP8SAx family of devices incorporates circuitry t | |||
| V54 | (40) | 13 | MOSTE | ||
| V55 | (3) | PLCC | 04+ | Normally, the B port operates at GTLP signal levels. The A-port and contr | |
| V56 | (27) | DIP | The Fairchild Switch FSTU16245 provides 16-bits of high- speed CMOS TTL | ||
| V57 | (11) | har | har | dc99 | 14-bit resolution with no missing codes Throughput: 250 kSPS INL: 0.4 L |
| V58 | (27) | The MAX 3000A architecture includes four dedicated inputs that can be us | |||
| V59 | (10) | PRINCE CORP | 20PIN-SOP | 06+ | • Fast I2C-bus controlled (max. 400 kHz) • PLL controlled soun |
| V5F | (1) | The AD8353 is fabricated on Analog Devices proprietary, high- performanc | |||
| V5N | (1) | STM | ＳＯＰ－１０ | 05+ | Either input can be driven to the Absolute Maximum Ratings limit without |
| V5R | (3) | The FAULT output is operational only if ENABLE is high. The outpu | |||
| V5S | (1) | 500 | 2003 | N-Channel Synchronous MOSFET Driver Programmable Timeout Reverse Inducto | |
| V5V | (1) | 1LC3 | The 556C/W for the SOTC23 package assumes the use of the recommen | ||
| V60 | (28) | H | 01+ | PLCC-28 | ZC is a CMOS input structure. It receives AC line fre- quency and generat |
| V61 | (62) | N/A | DIP24 | 06+ | The second contributor to the constantly varying pixel offsets is the fa |
| V62 | (77) | MOSEL | SOP32 | Full duplex UART Three 16-bit timers each with two 16-bit registers sup | |
| V63 | (95) | SOT-23 | VCC to GND PGND to GND FB to GND SHDN to GND LX to GND Peak LX Curren | ||
| V64 | (2) | GND - is the low voltage supply return for the +15V. All bypassing of th | |||
| V65 | (3) | SMD | 98 | Turn-On Time: In the circuit of Figure 1, turning Q1 on applies a low vol | |
| V66 | (6) | The V660LA100B-01 is a low skew, high performance 1-to-5 different | |||
| V67 | (3) | The operational overview diagram in Figure 2 illustrates the operation of | |||
| V68 | (18) | N/A | SOP | 07+ | • True single-chip tuner • Single 3.3V supply v |
| V69 | (3) | 05+ | SOP/32 | The Harris CD74HC688 and CD74HCT688 are 8-bit magnitude comparators des | |
| V6C | (3) | MOT | PLCC44 | 06+ | This product can also be used on telephone, signal/data lines, security, |
| V6D | (3) | MOT | 02+ | PLCC44 | Specifications Outline Dimensions Pin Connections and Short Description |
| V7- | (36) | Addresses and data needed for the programming and erase operations are | |||
| V70 | (39) | N/A | SMD | 03+ | The U6209B is controlled via a 2-wire I2C bus format by feeding data and |
| V71 | (7) | HARRIS | SOP | 03+ | 868MHz, 902-928MHz Bands OOK and FSK Demodulation Low Current Consump |
| V72 | (2) | The negative terminal of the battery pack (negative terminal available to | |||
| V73 | (91) | AMS | 9010+ | PLCC84 | Pericom Semiconductors PI5C16212 is a 24-bit bus exchange switches desig |
| V74 | (18) | N/A | SOP | 07+ | HIGH voltage level steady state. LOW voltage level steady sta |
| V75 | (9) | ||||
| V76 | (1) | Finally, the CY7C371i features a very simple timing model. Unlike other h | |||
| V77 | (1) | LMD is the last measured discharge capacity of the battery. On initializa | |||
| V78 | (16) | H | 01+ | PLCC-28 | Right channel serial data input. Both LDATA and RDATA are assumed to be M |
| V79 | (2) | DIP-L24P | 38503 | PHI | The CY7C291A is a high-performance 2K-word by 8-bit CMOS PROM. It is pa |
| V7A | (4) | bel | SOP | 548 | |
| V7M | (1) | The output capacitor and ESR comprise a zero in the loop transfer functi | |||
| V7S | (1) | NOTES: 1. Dimensions are in inches. 2. Metric equivalents ar | |||
| V-8 | (2) | TEMIC | 98+ | QFP44 | This represents a 21.6C temperature rise (36C/W *0.6W) for a die |
| V8- | (1) | N/A | PQFP-52 | 98 | This amplifier is designed with compensation to negate the package |
| V80 | (17) | PHILIPS | 06+ | 1600 | The CA3094 offers a unique combination of characteristics that suit it |
| V81 | (4) | NEC | |||
| V82 | (21) | VIS | 05+ | BGA | Input Voltage Noise Non-Inverting Input Current Noise Inverting Input |
| V83 | (6) | NS | 06+ | SOT23/6 | Application Notes Differences between VPX 3220A and VPX 322xD Impact to |
| V84 | (9) | Testing of the switching parameters is modeled after testing methods spec | |||
| V85 | (8) | VLSI | PLCC | are capable of directly interfacing with a wide variety of I/O devices, | |
| V86 | (224) | The V86999CAXHM consists of two 12-bit registers, control logic an | |||
| V87 | (1) | PHI | PLCC-L68P | 06+ | HyperPHY channels can be used as the serial backplane interface b |
| V88 | (1) | ASAT | 00+ | SSOP-16 | This automotive grade product provides a versatile interface betw |
| V89 | (2) | 84 | TEST RESET: An asynchronous reset signal (active low) which initializes t | ||
| V8A | (1) | † Stresses beyond those listed under absolute maximum ratings may c | |||
| V8C | (2) | PLCC44 | 02/03+ | STOPPED-CLOCK OPERATION The PCM58P is normally operated with a continuou | |
| V8H | (1) | RESET: A RESET input pin is provided to ease some system applications. Wh | |||
| V8Z | (8) | LITTELFUSE | 0718+ | Variable clock Bidirectional (TTL compatible input and Totem-pole output) | |
| V9- | (2) | N/A | PLCC-44 | 99 | Driver (Tx) outputs are short circuit protected, even for voltages excee |
| V90 | (4) | PLCC | 04+ | Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output | |
| V91 | (7) | ST | SOP | 1998年 | An input pin (RESET#) resets the chip. This pin has hysteresis and is ac |
| V92 | (3) | The PT4310 modules are a low-power series of isolated DC/DC conve | |||
| V93 | (1) | Siemens SSRs are available in a 6- or 8-pin through-hole DIP or in gull- | |||
| V94 | (5) | PRIMCE | SOP-20 | 02+ | The MAX2622/MAX2623/MAX2624 VCOs are imple- mented as an LC oscillator to |
| V96 | (24) | H | 01+ | PLCC-28 | Fabricated on an advanced SRAM process Available in a variety of package |
| V97 | (1) | Note 4. Regulation is measured at constant junction temperature, using pu | |||
| V98 | (2) | PLCC | 04+ | Four synchronous outputs Selectable divider/multiplier Output Enable con | |
| V99 | (7) | 08+ | The device also features split output bank power supplies which enable | ||
| V9M | (7) | 3.3 Electrical performance characteristics and postirradiation par | |||
| VA- | (10) | CERATECH | NA | Reference clock. REFCLK is an external 125 MHz input clock that synchroni | |
| VA0 | (11) | SOP14 | 06+ | ||
| VA1 | (30) | abelec | abelec | dc95 | For packing material that is returned to us unsorted or which we are no |
| VA2 | (15) | egg | egg | dc95 | Thispreliminarydatasheetcontainsthe specifications for the Advanced Boot |
| VA3 | (1) | SOP14 | 06+ | The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs | |
| VA4 | (1) | VTC | DIP | N/A | The base timer is an 8-bit counter with a 1MHz clock source. The base time |
| VA5 | (3) | 06+ | The SN65LV1023A and SN65LV1224A are a 10-bit serializer/deserializer chip | ||
| VA7 | (39) | N/A | SOT23/6 | 05+ | Transmit synchronizing signal input. The PCM output signal from the PCMOU |
| VA8 | (8) | INTEL | CPGA168金 | 95/96+ | 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ |
| VA9 | (1) | • True Dual-Ported memory cells which allow simulta- neous a | |||
| VAA | (6) | PHILIPS | QFP1420-100 | 01+ | The UDA1384 is a single-chip consisting of 4 plus 1 Analog-to-Digital Con |
| VAB | (7) | A 200-kHz push-pull application circuit with a full-wave rectifier is sho | |||
| VAC | (12) | CY | PGA | This pin represents the output of the charge pump. The voltage at this pi | |
| VAD | (9) | VAD | DIP | The H8S/2000 CPU can execute basic instructions in one state, and is prov | |
| VAE | (16) | The ATR4258 implements an AM up/down-conversion reception path from the R | |||
| VAF | (10) | If the BYTE pin is set at logic 0, the device is in byte configuration, a | |||
| VAH | (1) | Texas Instruments | 06+ | 2065 | Two on-chip current limit comparators provide dual level overcurrent circ |
| VAI | (1) | Each port independently collects statistical information using SNMP and th | |||
| VAL | (31) | LUCENT | PQFP | 1996 | The difference between TPS6202x and TPS62021 is the logic level of the MO |
| VAM | (15) | MC | - | − 15-kV − Human-Body Model Meets or Exceeds the Requirements | |
| VAN | (6) | BGA | 0221+ | The LM139 series consists of four independent precision voltage comparato | |
| VAO | (1) | *There is also an option for anAnti Reflection Coating. This will remove | |||
| VAP | (3) | ADI | 06+ | 500 | During steady-state operation for a typical switching cycle, the oscilla |
| VAR | (4) | ||||
| VAS | (1) | * Antiparallel diode for high frequency switching devices * Antis | |||
| VAT | (31) | MINI | 08+ | The product term select multiplexer (PTMUX) allocates the five product te | |
| VAW | (2) | PHILIPS | SOT | 05+ | 4.3 Screening. Screening shall be in accordance with MIL-PRF-19500 |
| VAY | (3) | MINI | 08+ | The small form factor and simple interface make the DataFlash Card ideal | |
| V-B | (1) | Analog-to-Digital Converters − 24-Bit Linear PCM or 1-Bit Di | |||
| VB- | (2) | 5. Applies to each output; each output has independent thermal shutdown; | |||
| VB0 | (25) | MOTOROLA | 02+ | QFP | The Dallas Semiconductor DS1804 is built to the highest quality standards |
| VB1 | (31) | VTC | QFP52 | No Connection A logic I/O port. External encode clock input or internal | |
| VB2 | (8) | SOP20 | 06+ | TX voice (Mic.) inputs, selectable by SW1 available for handsfree mic./ha | |
| VB3 | (10) | Infineon | 03+ | for this lower supply voltage operation, in which case the sensiti | |
| VB4 | (4) | • 4-bit I2C GPIO with interrupt and reset • Operating power su | |||
| VB5 | (2) | HOWA | DIP | 02+ | Multiply Accumulate Unit for fast signed multiply or mul- tiply-accumula |
| VB6 | (4) | SIEMENS | 07+ | Minimum Dielectric Strength, Input-Output Minimum Insulation Resistance, | |
| VB7 | (3) | N/A | 08+ | The transmitter converts electrical PECL compatible serial data (TD and | |
| VB9 | (10) | ST | TO220F | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All V | |
| VBB | (1) | 4.4.3.3 Group C inspection sample selection. Samples for subgroups | |||
| VBC | (1) | On the next clock rise the data presented to DQs and DQP[A:D] (or a subse | |||
| VBE | (4) | FUJI | 55 | MODULE | q Electrical characteristics of power circuit (Tc=Tj=25˚C, Vcc=15V) |
| VBG | (2) | STM | ＳＯＰ－１０ | 05+ | Current Output, Sourcing Current Output, Sinking Closed-Loop Output I |
| VBH | (2) | Jack(Available) | The MSAU300 converter is encapsulated in a low thermal resistance molding | ||
| VBI | (4) | The FSA2467 is a Quad Single Pole Double Throw (SPDT) analog switch. Th | |||
| VBJ | (1) | NOTE: Intersil Lead-Free products employ special lead-free material sets; | |||
| VBL | (1) | Since G6 and G7 are input only pins any attempt by the user to configure | |||
| VBM | (12) | since an approaching finger could be compensated for partially or entire | |||
| VBN | (1) | AD | SOT25 | 6+ | FEATURES HIGH SURGE CAPABILITY TRANSIL ARRAY IPP = 40 A (8/ |
| VBO | (107) | FUJI | 55 | MODULE | The VBO54-16NO7, VBO54-16NO7 series are optically coupled isolato |
| VBQ | (2) | SOP | The MAX3221 consists of one line driver, one line receiver, and a dual ch | ||
| VBS | (1) | The RC2207 has a typical drift specification of 20 ppm/C. The osci | |||
| V-C | (1) | The LNA has a 2.4dB typical noise figure and a -10dBm input third-order i | |||
| VC- | (99) | FUJITSU | 99+ | Ergonomics Convenient front access to USB, audio, and Sma | |
| VC/ | (1) | Bit 6 of the day byte is the frequency test bit. When the frequency test | |||
| VC0 | (139) | AVX | 06+ | The UC385 is a low dropout linear regulator providing a quick response to | |
| VC1 | (98) | AVX | 06+ | 16384 bits Electrically Programmable Read Only Memory (EPROM) communica | |
| VC2 | (126) | VLSI | PLCC84 | When CS is high, the device enters standby mode: the AS6UA5128 is guarant | |
| VC3 | (33) | N/A | 1206 | The host system can detect whether a program or erase operation is comp | |
| VC4 | (40) | AGR | TSSOP | N/A | During power on, RESET is asserted when supply voltage VDD becomes highe |
| VC5 | (83) | VLSI | PQFP | 1996 | Differential inputs indicate a loss of receive signal power. When ALOS+/- |
| VC6 | (12) | PHILIPS | 99+ | TSOP20 | Address, data inputs, and all control signals are synchronized to the inpu |
| VC7 | (35) | 94 | Products designated as Not Recommended for New Design may become o | ||
| VC8 | (19) | SIEMENS | 9838 | QFP | Power supply Output pin of internal constant-voltage circuit. Connects t |
| VC9 | (2) | N/A | N/A | N/A | Under the control of the output enable term, the I/O pin can function as |
| VCA | (92) | TI | TQFP | 04/ | The AD5258 provides a compact, nonvolatile 3 mm 4.9 mm packaged solutio |
| VCB | (12) | START-IN: This active low input initiates an addressing sequence. May be | |||
| VCC | (82) | N/A | UNITRODE | 04+ | |
| VCD | (9) | NEC | QFP | 1997 | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant |
| VCE | (10) | VITE | SOJ-4 | C Pinout and software compatible with single-power supply Flash d | |
| VCF | (4) | 3.3V Operation with 5V Tolerant Buffers ACPI 1.1, PC99/PC2001 Compliant | |||
| VCH | (5) | TOSHIBA | SOP | 93 | Max. UnitsConditions CCCVVGE = 0V, IC = 500µA CCC V/C VGE = 0V, I |
| VCI | (2) | infineon | TO263-7 | 05+ | ESD damage can range from subtle performance degradation to complete devi |
| VCK | (7) | KYOCERA | N/A | If VBatt > 28.5 V (typ.), the voltage limitation of the IC is reduced | |
| VCL | (2) | PHILIPS | 05+ | The 25-40 watts PKA 2000 series hybrid DC/DC power modules are especially | |
| VCM | (12) | N/A | Calibration Cycle Initiate. A minimum 80 input clock cycles logic low f | ||
| VCN | (5) | NOTE: EP circuits are designed to meet the DC specifications shown in the | |||
| VCO | (46) | zation has two (LDM, UDM), one per byte. DLL aligns DQ and DQS transiti | |||
| VCP | (6) | 8X8 | QFP208 | 00+ | When reading this manual, disregard information concerning the floating-po |
| VCQ | (1) | (AVIN = 12V, PVIN = 12V, VUVLO = VSTT = 3V, VCON = 3V, RRCOSC = 24kΩ | |||
| VCR | (18) | Matsushita | IC | DESCRIPTION The device is manufactured using high voltage Multi Epitaxi | |
| VCS | (5) | HOSONIC | SOP | 436 | An external resistor, RSET, connected to pin 6 is used to set all timing |
| VCT | (112) | MICRONAS | DIP64 | 02+ | Notes: 1. These ratings are limiting values above which the serviceabilit |
| VCU | (22) | ITT | 01+ | PLCC44 | A problem arises in a CPE where the CAS detector is connected only to the |
| VCV | (4) | 3. This input current only exists when the voltage at any of the input le | |||
| VCX | (74) | FAIRCH | SMD | Noise on the transmission media is rejected by the receiver squelch cir | |
| VCY | (2) | CY | 03+ | ||
| V-D | (31) | Vishay Dale Models CCF55 and CCF60 are available in the standard 96 resi | |||
| VD- | (6) | NEC | 06+ | Control of the wiper (RW) position setting is accomplished via the two in | |
| VD0 | (6) | Freesals | SOP-16 | ||
| VD1 | (129) | FRECOM | N/A | Hynix HYMD232726A(L)8-M/K/H/L series is designed for high speed of up to | |
| VD2 | (96) | NSC | SOP | HR300 Series™ DC/DC converters combine the small size and high rel | |
| VD3 | (7) | The +5V Return (pin 6) and +3.3V Return (pin 9) are connected internal to | |||
| VD4 | (2) | The MAX1790/MAX8715 boost converters incorporate high-performance (at 1.2 | |||
| VD5 | (19) | N/A | N/A | N/A | The Unicorn II chipset is designed to simplify the development of low-c |
| VD7 | (5) | Converts a High-level analog input voltage into a floating proportional | |||
| VD8 | (1) | NEC | 0632+ | • Array Format: 1,280H x 1,024 V (1,310,720 pixels) • Pixel | |
| VD9 | (1) | Ultrasonically bonded leads and controlled die mount techniques are util | |||
| VDA | (7) | PHI | QFP64 | 06+ | SPI or EEPROM interfaces provide easy programming of the on-chip 802.1p |
| VDB | (1) | BMC | QFP | 1996 | This input is programmable. It functions as a read-write input R/W and ca |
| VDC | (1) | When executing a jump instruction, conditional skip ex- ecution, loading | |||
| VDD | (5) | N/A | Data Bus Enable: After A2CA0, CE, BYTE and R/W are set up, DBEN may be st | ||
| VDE | (1) | SHINDENGEN | SOD-6 | 04+ | The ESR of the required capacitor must be less than, or equal to 50mT |
| VDF | (1) | UBE | BGA-6 | 07+/08+ | 1. Life support devices or systems are devices or systems which, |
| VDG | (2) | Integral Nonlinearity (INL) 1, 2 Integral Nonlinearity (INL | |||
| VDI | (13) | IXYS | This CMOS device is designed for switching PCM-encoded voice or da | ||
| VDL | (3) | ||||
| VDN | (1) | STM | 652 | The actual completion of the nonvolatile write is asynchro- nous with t | |
| VDO | (20) | ELMOS | SSOP-36 | Input Specifications Voltage range Filter Isolation Specifications Rat | |
| VDP | (35) | MICRONAS | DIP64 | 03+ | DEVICE OPERATION The operating modes of the M27C801 are listed in the O |
| VDQ | (1) | Linux Operating System One of the distributions of Linux One of the dist | |||
| VDR | (2) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Sourc | |||
| VDS | (25) | ADI | 07+ | Read-Write(1,2)LL Fast-Page-Mode Read: EDO(2) 1st Cycle:LH∅L &nbs | |
| VDU | (23) | ITT | 06+ | The 128-pin version of the CY7C646xx brings out the full 8051 address and | |
| VDX | (3) | • High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns • Battery | |||
| VDZ | (14) | ROHM | 0507 | The HC595 devices contain an 8-bit serial-in, parallel-out shift regist | |
| VE- | (13) | TAKAMISAWA | RELAY | Synchronous detect. SYNC is asserted high upon detection of the K28.5 cha | |
| VE0 | (79) | SILI | • Four Crystal modes, up to 40 MHz • 4x Phase Lock Loop (PL | ||
| VE1 | (56) | tpc | tpc | dc03 | Address Inputs: Provide the row address for Active commands, and the colu |
| VE2 | (22) | tpc | tpc | dc03 | The triple driver IC includes three non-inverted and current-limited outp |
| VE3 | (2) | When writing data to the memory, the device in- serts an acknowledge bi | |||
| VE4 | (4) | INFINEON | SOP-14 | 04 | (0) After power on, the first integration scan is not guaranteed correct. |
| VE5 | (2) | S | . | The Intel 87C54 is a single-chip control-oriented microcontroller which i | |
| VE6 | (1) | FEATURES l Low power loss, high efficiency l Low forward voltage drop l | |||
| VE8 | (11) | RALTRON ELECTRONICS | 05+ | ||
| VE9 | (1) | Continuous Drain Current, V GS @ 4.5V Continuous Drain Current, V GS @ | |||
| VEB | (1) | CET | SMD-20 | The Line State output pins LineState[1:0] are driven by combi- national | |
| VEC | (16) | ZIOLG | DIP | 98 | Micropower: 95µA Supply Current Max Low Input Offset Voltage: 100&m |
| VED | (1) | In applications where the input to the WDI pin may be active (transitioni | |||
| VEF | (11) | ESD damage can range from subtle performance degradation to complete devic | |||
| VEH | (2) | Wide Operating VIN Range: Up to 80V Rugged Architecture Tolerant of 100V | |||
| VEK | (1) | Stresses beyond those listed under "absolute maximum ratings" m | |||
| VEL | (1) | The AT40KAL, AT6000 and FPSLIC families are capable of implementing Cache | |||
| VEM | (1) | 1. Less sensitive to fluorescent lamp driven by inverter 2. Impr | |||
| VEN | (1) | BUFFALO | QFP | 00+ | Input and output signals to and from the internal clock generation circui |
| VER | (27) | BGA | 2004 | The transponder is the mobile part of the closed coupled identification s | |
| VES | (48) | VLSI | 96 | The FAN2502/03 is designed to supply 150mA at the specified output | |
| VEY | (2) | SANYO | Die nachfolgend angefhrten R/T-Kennlinien sind auf den Widerstandswert 25 | ||
| VF- | (3) | DATEL | CDIP | The AT91X40 Series Microcontrollers integrate an ARM7TDMI with its embedd | |
| VF0 | (10) | 2004PB | is the case then the N-Channel MOSFET is fully enhanced and the CTIM capa | ||
| VF1 | (44) | 07+ | RESET is asserted and the condition is latched until VHTH > VTH. Reset | ||
| VF2 | (7) | Vishay | When VCC is between 0 and 1.5 V, the devices are in the high-impedance st | ||
| VF3 | (13) | VALPEX | 晶振 | The VF315P-3.6864MHZ provides high security, low cost, and ease of implem | |
| VF4 | (27) | HONEYWELL | TO-92 | 06+ | The Am29F010A is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131, |
| VF5 | (21) | DIODE | By substituting the attenuated values of Vd and Id for the Vi and Ii in | ||
| VF6 | (2) | Current-mode PWM Controller High-current output drive suitable for Power | |||
| VF7 | (11) | Note: These are stress ratings only. Stresses exceeding the range specifie | |||
| VF8 | (2) | DELTA | 00 | Fourth Generation HEXFETs from International Rectifier utilize advanced | |
| VF9 | (8) | VALPEY | SMD晶振 | 00+ | When executing a jump instruction, conditional skip execution, loading P |
| VFA | (9) | Mornsun | 07+ | Note 4: For a power supply of 5V 10% the worst case output voltages (VOH, | |
| VFB | (1) | Because the VFB240458F is a common I/O device, data should not be driven | |||
| VFC | (114) | BB | DIP | 8917 | When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE |
| VFD | (3) | dc | 2.9V to 14V input voltage range 400kHz oscillator frequency PWM curren | ||
| VFF | (1) | The basic method of communication for the device is established by @ | |||
| VFH | (1) | Transmit Ready A-B (active low) - This function is associ- ated with 44 | |||
| VFI | (6) | 21 | ZILOG | The bandwidth of KESRX05 is set by the external ceramic filter CF1. Imp | |
| VFM | (5) | The D2Pak is a surface mount power package capable of accommodating die | |||
| VFP | (2) | The g-cell is a mechanical structure formed from semiconductor m | |||
| VFQ | (6) | DATEL | 101 | 01+ | The HOLTEKs HT93LC46/56/66 is a 1K/2K/4K- bit low voltage nonvolatile, se |
| VFR | (2) | • This unit is designed to operate on 12 volts DC, negative ground e | |||
| VFS | (6) | MURATAELEC | 04+ | To read the output of the TMS29xF040, a low-level logic signal is applied | |
| VFT | (10) | ASI | Memory interface Can address up to 64 K bytes of External Program | ||
| VG- | (28) | NEC | 98 | TQFP | Hynix HYMD212G726(L)S4M-K/H/L series is designed for high speed of up to |
| VG0 | (56) | HOKURIKU | 3X3-2K | KEY1~KEY8 all function as trigger keys. By mask option, the HT812L0 provi | |
| VG1 | (25) | WJ | O7+ | Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS | |
| VG2 | (55) | N/A | 02+ | PLCC-44 | INTERFACE RESET: The RST pin is used for both FWH/LPC and A/A Mux interf |
| VG3 | (30) | TSOP/54 | 03+ | The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency | |
| VG4 | (35) | ||||
| VG5 | (5) | 5000 | N/A | 散新 | The Unicorn II chipset is designed to simplify the development of low-c |
| VG6 | (3) | • Automatic power-down • Expandable data bus to 32/36 bits or | |||
| VG7 | (2) | N/A | SOP8 | The LM4924 is a Output Capacitor-Less (OCL) stereo head- phone amplifier | |
| VG8 | (1) | LNLIFE | DIP16 | 2007+ | Pulled-high, this pin is a Schmitt trigger input structure. Active low. Ap |
| VG9 | (4) | MOT | SMD | 00+ | The ADC14L020 is a low power monolithic CMOS analog- to-digital convert |
| VGA | (6) | CALIFORNIA | SSOP24L | 0521+ | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis |
| VGC | (28) | VITESSE | QFP | 00+ | These octal D-type transparent latches feature 3-state outputs designed |
| VGE | (1) | The device is made up of two sections: a cascaded antialiasing + switch | |||
| VGF | (21) | VGF | TO-220 | 2003 | [CAUTION] The specifications on this data book are only given for |
| VGL | (19) | Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative p | |||
| VGO | (8) | • Especially suitable for applications from 400 nm to 1100 | |||
| VGP | (1) | EPSON | 04+ | QFP/208 | Settling Time (ts). The delay between the time that a track-and-hold circ |
| VGS | (36) | VITESSE | QFP | 11.1 United States export laws and regulations prohibit the exportation o | |
| VGT | (75) | TI | PQFP120 | This surface mountable 1 watt Zener diode series is electrically equivalen | |
| VGV | (1) | • Three isolated elements are contained in one package, allowing &n | |||
| VH0 | (3) | WALSIN | 3.2 KSO8~15 These pins are direct output from the 8051 Port2 and dedicate | ||
| VH1 | (7) | varo | n/a | Power dissipation at 25ºC: 1.0 watts (also see derating in Figure 1 | |
| VH2 | (6) | ST | SSOP | 06+ | High-side gate-drive floating supply Voltage. The bootstrap capacitor con |
| VH3 | (4) | JCI | SMD | If the part is attached in a reflow oven, the temperature ramp rate shoul | |
| VH4 | (8) | MOT | 07+ | Bidirectional I/O lines. Software instructions determine the CMOS out- pu | |
| VH5 | (2) | ST | TO-220 | 00+ | This pin is the voltage supply pin for the control circuitry of the device |
| VH6 | (1) | TI | TSSOP48 | 00+ | Designed for general purpose amplifier and low speed switching ap |
| VH7 | (2) | TI | TSSOP48 | 00+ | Cycle-by-cycle current limiting, under-voltage lockout with hyster |
| VH8 | (4) | ASI | (LX)high-frequency | Celeritek reserves the right to make changes without further notice to an | |
| VH9 | (3) | TI | 00+ | TSSOP48 | Notes: 1. CL = Load capacitance: includes jig and probe capacitance. |
| VHA | (1) | SOP-8 | 2004 | † VHA-25I equivalent no. 4040065. ‡ Models with a slash (/) | |
| VHB | (11) | ASI | (LX)high-frequency | 1. Dimension are in inches. 2. Metric equivalents are given f | |
| VHC | (127) | TOS | SMD | 97+ | Synchronous byte write enables. Each 9-bit byte has its own active low byt |
| VHD | (5) | NULL | N/A | The MAX7447 processes S-Video and CVBS video sig- nals. The video output | |
| VHE | (12) | STM | 6750 | ¡In the absence of confirmation by device specification shee | |
| VHF | (91) | IXYS | COL[2]; Disables Management Interface and selects the Full Duplex operati | ||
| VHG | (3) | 03 | Analog composite video signal output or Cb or B signal output current dri | ||
| VHI | (38) | CONEXANT | QFP | 9906+ | Posistive excursions of input voltage may exceed the power supply level. |
| VHJ | (3) | VHJ | SOP | 0 | 1.1 GHz Toggle Frequency Supply Voltage 4.5 to 5.5 V Low Power 4.0 mA Ty |
| VHK | (10) | N/A | ++ | DIP18 | Good PC board layout is an essential part of an RF cir- cuits design. The |
| VHM | (1) | IXYS | Day of the Week Register (DW) This register provides a Day of the Week s | ||
| VHO | (14) | IXYS | DIO+THY | The Fairchild Switch FST16209 provides 18-bits of high- speed CMOS TTL- | |
| VHP | (10) | MINI | 08+ | Guaranteed Zero Reading for 0V Input on All Scales True Polarity at Zero | |
| VHR | (13) | JST | 2008 | 800 | There are two popular conventions for establishing the rela- tive phasin |
| VHS | (1) | element. Because the PMOS pass element behaves as a low-value resistor, | |||
| VHT | (4) | TOSHIBA | TSOP-14P | 6+ | See the Terminology section. These specifications do include full tempera |
| VHV | (4) | N/A | XC4000-family devices have generous routing resources to accommodate th | ||
| VI- | (11779) | VICOR | SOP | The current drive capability of the buffered Tx and Ty outputs exceeds | |
| VI/ | (2) | Note that full duplex mode is meaningful only if the media selection is UT | |||
| VI0 | (10) | 98+ | QFP | 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC. 3. These | |
| VI1 | (3) | GXL TONE | SOIC32 | If the centering error is less than 25 ppm, no adjustment is needed. If | |
| VI2 | (50) | 04+ | Decoupling capacitors of 0.01 µF should be connected between each | ||
| VI3 | (9) | The ICS91309 is a high performance, low skew, low jitter zero delay buff | |||
| VI4 | (36) | DIP | This MOSFET is an enhancement-mode silicon-gate power field effect tran | ||
| VI5 | (5) | 91+ | QFP | SELECTABLE INPUT DATA STROBE The Transmitter input data edge strobe can | |
| VI6 | (17) | 日立 | DIP | 99 | 3. When operating the ADS-929 from 12V supplies, do not drive ext |
| VI7 | (3) | The Current Transfer Ratio (CTR) ranges from 100% to 200%. It also has an | |||
| VI8 | (6) | 99 | The HA-5020 is a wide bandwidth, high slew rate amplifier optimized for v | ||
| VI9 | (9) | 00+ | QFP | THESE MATERIALS ARE PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER E | |
| VIA | (32) | VIA | BGA | 03+ | |
| VIB | (4) | 98+ | Auxiliary receive filter output. The output signal is inverted with respe | ||
| VIC | (75) | Sirenza Microdevices SBB-2089 is a high performance InGaP HBT MMIC amplif | |||
| VID | (32) | Combined byte-wide specification (previously 290605) with this document | |||
| VIE | (2) | N/A | The ST7263 Microcontrollers form a sub family of the ST7 dedicated to U | ||
| VIG | (2) | AMIS | 07+ | Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In | |
| VIH | (2) | DG | SMD | † Stresses beyond those listed under absolute maximum ratings may c | |
| VII | (15) | N/A | Note: 1. H=VIH, L=VIL, X=don't care(VIH or VIL) 2. UB, LB(Upper, Lower | ||
| VIJ | (24) | 5V TOLERANT INPUTS HIGH SPEED: tPD = 4.2ns (MAX.) at VCC = 3V POWER DO | |||
| VIK | (6) | 5 | SOP | The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locke | |
| VIL | (7) | DIP | † Stresses beyond those listed under absolute maximum ratings may c | ||
| VIM | (11) | TQFP32 | 2007+ | Serial interface • SIO0 : 8-bit synchronous serial interface | |
| VIN | (13) | 66 | ST | 03+ | Note 3: Minimum input voltage is defined as the voltage where the interna |
| VIO | (12) | IXYS | • Battery Powered Systems • Cordless Telephones • Radio C | ||
| VIP | (162) | 7500 | 国半 | 06+ | The ADSP-TS202S processors external port provides the DSPs interface to |
| VIR | (1) | The PCS-CDMA transmit chain provides excellent Adjacent Channel Power Re | |||
| VIS | (10) | 07+ | Access to internal peripherals is accomplished in three CPU T-states (cl | ||
| VIT | (9) | ZILOG | DIP | 99+ | The circuit board used in the final application should be generated |
| VIV | (1) | 652 | Note 1. 100KEP circuits are designed to meet the DC specifications shown | ||
| VIX | (1) | N/A | N/A | 04+ | The Address inputs are used to set the least significant 3 bits of |
| V-J | (1) | This block generates the system timing and control signal supplied to the | |||
| VJ0 | (815) | vishay-gro | n/a | NOTES:2606 tbl 01 1. Stresses greater than those listed under ABSOLUTE M | |
| VJ1 | (930) | VIT | 06+ | 135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch 500 mA Continu | |
| VJ2 | (42) | avx | avx | dc04 | The following briefly describes a procedure for evaluating the high effic |
| VJ3 | (5) | The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 | |||
| VJ4 | (1) | The PVN013 Series Photovoltaic Relay at 100 milliohms features the lowe | |||
| VJ5 | (8) | LEXMRK | 07+ | The subsequent analog signal is sent to the on-chip line driver where th | |
| VJ6 | (2) | DSI | The typical values of the input currents are 25 mA and are equally large | ||
| VJ7 | (19) | vish | vish | dc04 | The IC operates from a 3V regu- lated supply, making it ideal for use w |
| VJ9 | (61) | 0805-104M | 12. Measured by the voltage drop between A and B pins at the indicated cu | ||
| VJA | (9) | In contrast to the BTS 7710 G, which consists of the same chips in an P-D | |||
| VJC | (1) | Note 6: Total latency for the channel link chipset is a function of clock | |||
| VJI | (1) | All voltages are measured with respect to GND, unless otherwise sp | |||
| VJO | (1) | Modem Control Output For external modem, these pins are bit7~4 of the mo | |||
| VJP | (1) | 200 | Gehäusebauform: P-LCC-2 Gehäusefarbe: weiß als optisch | ||
| VJS | (1) | VTC | CDIP-24 | Panel attachment VJS610DU has hole for panel attachment. Please be sure | |
| VJX | (1) | • Data transfer may be initiated only when the bus is not b | |||
| VJY | (5) | • Command/Address/Data Multiplexed I/O Port • Hardware Data | |||
| VK- | (9) | HS | 97+ | HIGH SPEED: tPD= 20 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC | |
| VK0 | (20) | ST | SOP-3.9-8P | 6+ | * On products compliant to MIL-PRF-38535, this parameter is not productio |
| VK1 | (9) | VISHAY | 04+ | The READ instruction is the only instruction that outputs serial data o | |
| VK2 | (7) | vikey | vikey | dc94 | The UCODE HSL IC (UCODE High frequency Smart Label) is a dedicated chip fo |
| VK3 | (1) | Advanced HEXFET® Power MOSFETs from International Rectifier utilize a | |||
| VK4 | (1) | MOTOROLA | 02+ | QFP | In addition to the Voltage Identification, there are several sig- nals t |
| VK5 | (5) | JCI | . | The 128-bit instruction line, which can contain up to four 32-bit instru | |
| VK6 | (1) | N/A | N/A | N/A | DESCRIPTION The IS66_ series are optically coupled isolato |
| VK7 | (1) | 04+ | Frequency, Channel#1/Channel#2 Modulation Frequency deviation Max. RF | ||
| VK8 | (1) | MOTOROLA | 02+ | QFP | This product is intended for clock generation. It has low output jitter |
| VKA | (20) | N/A | The ADM integrates a standard 40- or 44-pin female connector for easy a | ||
| VKB | (6) | • Robust High Voltage Termination • Avalanc he Energy Specifi | |||
| VKC | (1) | Erasable windowed versions (Q3) are available for use with a range of C | |||
| VKF | (5) | IXYS | Figure 4 shows the timing of the encoder output in long frame mod | ||
| VKI | (4) | vikey | vikey | dc98 | 1. StarTech PPI Card memiliki konektor DB25 Female yang berisi 24 port eks |
| VKM | (3) | IXYS | Because of the fast rise-time of the ESD transient, placement of PulseGu | ||
| VKO | (6) | N/A | Register-usage rules influence placement of input and results within the | ||
| VKP | (23) | N/A | Designed for use in battery-powered applications, the FAN2001/ FAN2002 | ||
| VKS | (1) | "Features 1) Built-in overcurrent protection circuit and thermal shu | |||
| VL- | (1) | N/A | n Versatile easy to use instruction set n 1 µs instruction cycle | ||
| VL0 | (4) | MICROCHI | 111 | SMD28 | • IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability Us |
| VL1 | (35) | CERATECH | NOTES: 1. Terminal 1, emitter; terminal 2, base; terminal 3, coll | ||
| VL2 | (14) | The AUP family is TI's premier solution to the industry's low-power needs | |||
| VL3 | (3) | VLSI | PLCC-84 | 07+/08+ | The FDS6982AS is designed to replace two single SO- 8 MOSFETs and Schottk |
| VL4 | (8) | N/A | VL | 04+ | The TPR 1000 is a high power COMMON BASE bipolar transistor. It is desig |
| VL5 | (1) | The following are trademarks of Skyworks Solutions, Inc.: Skyworks®, t | |||
| VL6 | (30) | 07+ | PLCC | The TMS41x809 series is a set of high-speed, 16 777 216-bit dynamic ran | |
| VL7 | (7) | VHK | 93 | Description The 14.22 mm (0.56 inch) LED dual digit seven segment displa | |
| VL8 | (209) | vlsi | vlsi | dc89 | In the following application circuits: *1 : For heavy loading application |
| VL9 | (1) | N/A | N/A | 99+ | If your computer is not connected to the Internet, NIST also provides Dial |
| VLA | (7) | N/A | N/A | N/A | • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 180 MHz Ma |
| VLB | (10) | ASI | 2008 | where VDEL is in Volts, and RDEL is in Ohms and tDELAY is in seconds. D | |
| VLC | (47) | TDK | Features • 2.2 GHz operation • 10/11 prescaler | ||
| VLD | (3) | ALCATEL | Guaranteed Logic HIGH Level Guaranteed Logic LOW Level Standard Input(4) | ||
| VLF | (145) | N/A | With every advance of this magnitude, there arise new considerations th | ||
| VLG | (5) | The K6L0908C2A families are fabricated by SAMSUNGs advanced CMOS p | |||
| VLI | (2) | ADC CHANNEL No Missing Codes1 Resolution Output No | |||
| VLK | (1) | OTAX | 07+ | The HCT245 devices allow data transmission from the A bus to the B bus | |
| VLM | (6) | 9 | The HYM72V64656T8 H-series are high speed 3.3-Volt synchronous dynamic RAM | ||
| VLN | (3) | The device has two supply voltages. VCC is designed for 3-V to 3.6-V ope | |||
| VLP | (32) | TDK | 5610 | 07/环保 | power consumption by 99% when addresses are not toggling. The device ca |
| VLR | (6) | RAYCHEM | RAYCHEM | 08+ | The HY51V(S)16400HG/HGL is the new generation dynamic RAM organized 4,194, |
| VLS | (5) | vlsi | vlsi | dc92 | The HEF4049B provides six inverting buffers with high current output ca |
| VLT | (6) | EOS | 04+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| VLU | (1) | GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to the gate(s) of t | |||
| VLW | (2) | vishay-gro | n/a | Out Short Circuit to GND Duration (VIN< 12V)...Continuous Out Short Ci | |
| VLX | (4) | XR | DIP | 06+ | The DS1481 also supports overdrive communication with overdrive capable |
| V-M | (1) | SOP 2.5.9Process critical and key parameters 0076604 Process Qualificatio | |||
| VM- | (4) | KONG | 1450 | ¡In the absence of confirmation by device specificati | |
| VM0 | (8) | VLSI | . | The V62C51864 is a 65,536-bit static random access memory organi | |
| VM1 | (27) | VM | 06+ | 500 | Inspection of this figure shows that the maximum current that the |
| VM2 | (33) | 150 | DIP | The HYM71V633201 H-Series are Dual In-line Memory Modules suitable for eas | |
| VM3 | (57) | 95 | SOP | Aluminum front panel 15" high brightness TFT color panel display | |
| VM4 | (8) | N/A | 06+ | 500 | NOTES: 1. Dimension are in inches. 2. Metric equivalents a |
| VM5 | (35) | SAMS | 模块 | N/A | A: The value of R JA is measured with the device mounted on 1in2 FR-4 boar |
| VM6 | (29) | TI | DIP28 | 04+/05+/06+/07+ | The B-port interfaces to Backplane Transceiver Logic (See the IEEE 1194. |
| VM7 | (59) | SOP | N/A | Section 4, Support: − added Section 4.1, Notices Concerning JTAG | |
| VM8 | (23) | VTC | . | The ADF4360-6 is a fully integrated integer-N synthesizer and voltage co | |
| VM9 | (6) | ST | TO220-5 | 05+ | (1) LED CURRENT CONTROL The NJU6052 incorporates the LED current c |
| VMA | (1) | Serial expansion is accomplished by tying the data inputs of one device | |||
| VMB | (2) | ASI | 00+ | N/A | TINI platform details can be found at www.maxim-ic.com/TINI. The TINI Spe |
| VMC | (7) | ON | 07+ | (1)Consult factory for test procedure. The reed switch shall be pl | |
| VMD | (1) | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (tu | |||
| VME | (16) | PLX | PLCC28 | 05+ | The analog front end features four single-ended input channels with unip |
| VMF | (3) | ALPHA | 0221+ | For the Read and all four Write commands, the data stored within the co | |
| VMI | (7) | Fast throughput rate: 250 kSPS Specified for VDD of 2.35 V to 5.25 V Low | |||
| VMK | (6) | N/A | The MC74AC273/74ACT273 has eight edge-triggered DCtype flipCflops | ||
| VML | (1) | N/A | 0603LED | Sirenza Microdevices SVG-2066 is an IC based 6-bit digi- tal 31.5dB range | |
| VMM | (13) | IXYS | MODULE | 1.2 ARCHITECTURE The COP8SAx family is based on a modified Harvard archi | |
| VMO | (12) | IXYS | The internal circuit is composed of 2 stages including buffer output, w | ||
| VMP | (3) | tic | n/a | The Fairchild Semiconductors RMLA3565C is a single bias wideband low no | |
| VMS | (8) | VLSI | 1450 | Absolute Maximum Ratings indicate limits beyond which damage to the devic | |
| VMU | (1) | These power transistors are produced by PPC's DOUBLE DIFFUSED PLANAR pro | |||
| VMV | (2) | Tables 2 and 3 summarize the different behaviour and advantages of both | |||
| VMX | (1) | The uPG2158T5K is a GaAs MMIC for L,S-band SPDT Single Pole Double | |||
| VMZ | (2) | ROHM | SOT-723 | 05+ | Figure 2 illustrates a typical application circuit (output source |
| VN0 | (137) | Freescale has begun the transition of marking Printed Circuit Boards (PCB | |||
| VN1 | (71) | CERATECH | AD5382-5 is calibrated using an external 2.5 V reference. Temperat | ||
| VN2 | (64) | SI | TO-92 | 99+ | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| VN3 | (38) | ST | 7000 | Guaranteed Low Skew < 25ps (max) Very low duty cycle dis | |
| VN4 | (18) | VISHAY | TO-92 | 00+ | and NX26F041A offer 1M-bits and 4M-bits of Flash memory organized in se |
| VN5 | (22) | ST | The PI3C16215 is a 20-bit bus switch with low ON-State resistance. The bu | ||
| VN6 | (12) | SILICONIX | 00+ | Macrocells can individually be specified for high perfor- mance or | |
| VN7 | (42) | ST | SOP-8 | Intel Corporation assumes no responsibility for the use of any circuitry | |
| VN8 | (39) | VIA | BGA | 06+ | 4.3.2 Thermal response (∆VBE measurements). The∆VBE me |
| VN9 | (26) | 04+ | MASK-ROM PIN-OUT COMPATIBLE SUPPLY VOLTAGE C VCC= 2.7 to 3.6V for Read | ||
| VNA | (18) | MCL | SMD | 01+ | The VNA1 uses bus cycles of 8 bits each for commands, data, and addresses |
| VNB | (24) | ST | TO-263 D2PAK | 08+ | Maximum ratings are those values beyond which device damage can occur. M |
| VNC | (4) | SUPEPTEP | DIP | The 74ALVC245 is an octal transceiver featuring non-inverting 3-state b | |
| VND | (114) | sgs | sgs | dc02 | because the timing models of competing architectures are very complex a |
| VNE | (1) | The information provided herein is believed to be reliable at press time. | |||
| VNH | (11) | ST | 1560 | 05+ | The ISL6208 also features a three-state PWM input that, working together |
| VNI | (3) | SHARP | DIP-32 | 00 | If the password mode is enabled with PW_ON, read and write commands are |
| VNK | (2) | ST | TO | ||
| VNL | (1) | 1. Typical characteristics are at TA = 25oC.2. Fmax = 1/tRC . 3. These ar | |||
| VNN | (13) | ST | SOT-223 | 05+ | A write to either the external interrupt polarity register (EXTPOLAR) or |
| VNP | (44) | STM | ０８+ | The FB pin monitors the output supply voltage and signals the RESET outpu | |
| VNQ | (34) | ST | SOP-28 | 07+ | Operation is synchronous and the device is edge-triggered on the LOW to |
| VNR | (6) | tosh | tosh | dc04 | We constantly strive to improve the quality of all our products and docum |
| VNS | (27) | ST | SOP-8 | Dead-time control prevents shoot-through current from flowing through the | |
| VNV | (10) | STM | ＳＯＰ－１０ | 05+ | NOTES: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Int |
| VNW | (5) | ST | 06+ | In-system operation of the VNW100N04 is very similar to other RAM based | |
| VO/ | (1) | ||||
| VO0 | (1) | FEATURES Voltage Feedback, Rail-to-Rail Output Rated Settling Time to W | |||
| VO1 | (1) | Compliance with PCI Local Bus Specification revision 2.1 Complianc | |||
| VO2 | (1) | Room = 25C, Full = as determined by the operating suffix. Typical values | |||
| VO3 | (1) | Vishay | SMD-6, Option 7 | 08+ | The Modem Control Software runs entirely on the DMT Transceiver (no ext |
| VO4 | (2) | Vishay | DIP-31 | 08+ | Stresses beyond those listed under Absolute Maximum Ratings may cause per |
| VO5 | (1) | NA | 02+ | The melting temperature of solder is higher than the rated temper | |
| VO9 | (2) | HP | 04+ | "Features 1) Built-in overcurrent protection circuit and thermal shu | |
| VOA | (10) | The PCA9544A provides four interrupt inputs (one for each channel) and on | |||
| VOF | (22) | SAMSUNG | 01+ | Host clock frequency selection is achieved by applying the appropriate lo | |
| VOG | (1) | Information furnished by Analog Devices is believed to be accurate and r | |||
| VOI | (4) | ZILOG | PLCC44 | ||
| VOM | (1) | Note: Stresses greater than those listed under MAXIMUM RATINGS may caus | |||
| VOP | (1) | N/A | QFP | • Operating & StorageTemperature: -65oC to +175oC • DC | |
| VOS | (2) | When valid data on the TX pins detected, the jabber timer is started. I | |||
| VOU | (14) | sam | sam | dc00 | The SY88713V operates from a single +3.3V or +5V power supply, o |
| VOY | (1) | PHI | SOP28W | 06+ | NOTES 1. The difference between the measured and the ideal code width (VR |
| V-P | (4) | N/A | PACMAN™ POP™ Power247™ PowerSaver™ PowerTrench | ||
| VP- | (2) | 台湾 | DIOD | 00+ | The external resistors allow the user to accurately and independently se |
| VP0 | (123) | VLSI | 07+ | The LM105 series are positive voltage regulators similar to the LM100, | |
| VP1 | (121) | VOICEPUM | Stresses above those listed under Absolute Maximum Ratings may cause perm | ||
| VP2 | (364) | PHILIPS | BGA | 03+ | Output Bus Select. With this pin at a logic high, both the I and the Q |
| VP3 | (35) | SANYO | This new IRK series of MAGN-A-paks uses high voltage power diodes in two | ||
| VP4 | (100) | LSI | QFP | 1999 | Specifications Outline Dimensions Dimensions of Sensitive Area Positio |
| VP5 | (31) | GPS | QFP1010-44 | 97+ | Lead Temperature (1.6mm or 1/16 from case for 10s)+260C (1) Stresses be |
| VP6 | (3) | 7B2 | Members of the Texas Instruments Widebus™ Family State-of-the-Art | ||
| VP7 | (1) | N/A | QFP | 04+ | The internal data word address counter maintains the last address accesse |
| VP8 | (1) | N/A | N/A | N/A | Notes: 1. Clock on/off latency is defined as the number of rising edges o |
| VP9 | (4) | VLSI | PLCC | Cell balancing of each cell is performed via a cell bypass path, which is | |
| VPA | (21) | Bursts can be synchronized to external noise sources such as mains frequ | |||
| VPB | (3) | N/A | 25201008 | CASE: Hermetically sealed axial-lead glass DO-35 (DO-204AH) package TERM | |
| VPC | (54) | VPC | DIP | The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offe | |
| VPD | (10) | N/A | N/A | N/A | Clocks in the ispLSI 2064 and 2064A devices are se- lected using the de |
| VPE | (7) | HISENSE | 2006 | Positive digital supply pin for the ADC11DL066s output drivers. This pi | |
| VPF | (3) | TOSHIBA | BGA7*10 | 2004+ | 2. Chip operation is not guaranteed after access to any of the reserved d |
| VPH | (6) | MIT | 97+ | NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VD | |
| VPJ | (3) | SANYO | SIP | 2001 | < Keep safety first in your circuit designs! > Mitsubishi Electric |
| VPL | (4) | VPL | QFP100 | ||
| VPM | (12) | SANYO | DIP | No output filter required for inductive transducers Selectable gain of | |
| VPO | (13) | HAR | CAN | The Spartan-IIE family is a superior alternative to mask-programmed ASI | |
| VPP | (39) | MAGNETEK | n/a | 1. A17 is a NC for IDT70V3399. 2. All VDD pins must be connected to 3.3V | |
| VPR | (11) | 00+ | External DRAM is required only for full PerFlow fea- ture support (laye | ||
| VPS | (55) | ? | PDIP30 | 4L1 | †These options are available on some devices. Please see the table |
| VPT | (6) | The CM3004 is a very-low-dropout regulator that offers both fixed outpu | |||
| VPU | (6) | ELAN digital | CBGA64 | 0428+ | Hynix HYMD532M726(L)6-K/H/L series incorporates SPD(serial presence detect |
| VPV | (2) | Except the build-in USB 1.1 interface, the capability of cooperating with | |||
| VPX | (54) | 05+ | PLCC | When the configuration process is finished and the device starts up in | |
| VPZ | (1) | The MX826 is a µProcessor controlled full-duplex audio proc | |||
| VQ- | (4) | VAOEM | QFP | 05+ | Note 8: CIN, COUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors |
| VQ1 | (17) | N/A | N/A | N/A | Packaged in the SOD523 package this addition to the Zetex Schottky diode |
| VQ2 | (6) | 90+ | NOTES 1Typicals represent average readings at 25C and VDD = 5 V, VS | ||
| VQ3 | (4) | SILICONI | DIP14 | N/A | Assume that a manufacturers company ID value is 006035H and the 24-bit ext |
| VQ4 | (2) | LEXMARK | 07+ | The incoming bipolar PCM signal, which is attenuated and distorted by t | |
| VQ5 | (8) | LEXMARK | 07+ | NOTES: 1. This parameter is warranted but not production tested. The pro | |
| VQ6 | (2) | 00+ | Parameter VDD to GND VA, VB, VW to GND IMAX1 Digital Inputs and Output | ||
| VQ7 | (8) | 94 | The ispLSI 2096VL is a High Density Programmable Logic Device containin | ||
| VQ8 | (3) | TI | SOP | • Tri-State-Receiver Output, Weak Pull-up when in Shutdown | |
| VQA | (4) | toMOS relay has only 30 pA even with the rated load voltage of 80 V (AQ | |||
| VQB | (5) | tfk | tfk | dc94 | The IDT5T907 2.5V single data rate (SDR) clock buffer is a user-se |
| VQC | (2) | PANASONIC | QFP | 1999 | In addition, the oscillator and flip-flop sections have been enhanced to |
| VQD | (1) | AELTA | 模块 | 02+ | Each red, green and blue current output should have a load resistor conn |
| VQE | (3) | Isolated & Non-Isolated Hermetic Packages Output Voltages: +5V, +12 | |||
| VQF | (5) | INFINEON | QFN | 2002 | VGC =1.25V (measured to single-ended out- put) VGC =1.95V (measured to |
| VQP | (3) | A comprehensive evaluation system is available upon request from your loca | |||
| VQR | (5) | N/A | The attached spice model describes the typical electrical characteristics | ||
| VQX | (1) | DELTA | DIP-8 | 2004 | Note 1: All parts are 100% tested at +25C. Limits across the full temperat |
| VR- | (6) | SHINDENGEN | at the transistor level and verified through measurements made on fabric | ||
| VR0 | (6) | N/A | When the R and V inputs are equal in frequency and the phase of R | ||
| VR1 | (12) | TAIYO | Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS | ||
| VR2 | (22) | TI | TSSOP48 | 00+ | •Specimen : Paraformaldehyde-fixed, paraffin-embedded 1.0mm diameter |
| VR3 | (16) | VISHAY | O7+ | AS serves to demultiplex the address/data bus. The falling edge of AS lat | |
| VR4 | (4) | The SY88713V low-power limiting post amplifier is designed for u | |||
| VR5 | (4) | NEC | For use in low voltage, high frequency inverters, free wheeling, and po | ||
| VR6 | (10) | GULF | DO-15 | 2007 | The fast-access register file concept contains 32 x 8-bit general-purpose |
| VR8 | (3) | JCI | 04+ | As you can see, neither the software nor the hardware PC clock is suitable | |
| VR9 | (8) | Microchip | SOP-7.2-28P | 06+ | The FM809/810 are supervisor circuits that monitor power supply or othe |
| VRA | (15) | MORNSUN | 08+ | INTRODUCTION National Semiconductor (NSC) is committed to provide ap- p | |
| VRB | (21) | MORNSUN | ORG PACKING | 08+ | DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3 |
| VRC | (4) | H = HIGH Level (steady state), L = LOW Level (steady state) X = Irrelev | |||
| VRD | (7) | cqe | cqe | dc99 | Case: Similar to DO-214AA Terminals: Leads tin plated Thermal resistance |
| VRE | (17) | JAT | 1W-0.1R | 05+ | 1.0 Command A command sets the display mode and status of the VFD |
| VRF | (5) | HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC | |||
| VRI | (1) | The HT24LC08 is an 8K-bit serial read/write non-volatile memory device us | |||
| VRM | (6) | 3.3-V power. I/O 3.3-V circuit power terminals. A combination of high-fre | |||
| VRN | (1) | SPD127-222M SPD127-332M SPD127-472M SPD127-682M SPD127-103M SPD127-12 | |||
| VRP | (6) | ST | 07+ | C Standard specific digital picture carrier recovery: • ali | |
| VRS | (10) | YAGEO | SOP | 615 | Status output from this IC to indicate that the outputs have been disable |
| VRV | (4) | 01 | Series W. Series W are rugged, ceramic, cylindrically shaped elements | ||
| VRY | (3) | Shindengen | TO-269AA | Designed for 802.16 WiBro and dual mode applications with frequenc | |
| VS- | (16) | NS | This device has been especially designed to pro- tect subscriber line c | ||
| VS0 | (13) | NSC | QFP2828-160 | • Antenna is provided on board •The module is Max.4 dBm( Clas | |
| VS1 | (103) | 2008 | The Hitachi HN58S256A is a electrically erasable and programmable EEPROMs | ||
| VS2 | (25) | YCL | 0020+ | The device is available with an access time of 70, 90, or 120 ns. The d | |
| VS3 | (33) | NSC | QFP | VOLTAGE OUTPUT versus APPLIED DIFFERENTIAL PRESSURE The output vo | |
| VS4 | (12) | INTEL | BGA | 05+ | LSB means least significant bit. With the 5 V input range, one LSB |
| VS5 | (16) | SAM | QFP-100 | 94+ | NOTE: Intersil Pb-free plus anneal products employ special Pb-free materia |
| VS6 | (15) | VOSSEL | 04+ | Wide inductance range in small package. Flame retardant coa | |
| VS7 | (24) | 03+ | QFP-S48P | Notes:3. Pulsed measurement, PW 350 µs, duty cycle 2%. 1. Precau | |
| VS8 | (22) | VALENCE | PLCC28 | 0111+ | These versatile devices are useful for driving a wide range of loads in |
| VS9 | (8) | 97 | may be accessed by hardware or software operation. The hardware operatio | ||
| VSA | (3) | Theory of Operation The ADNS-2001 is based on Optical Navigation Techn | |||
| VSB | (42) | N/A | Bit 6 of the day byte is the frequency test bit. When the frequency test | ||
| VSC | (476) | 800 | vitesse | dc00 | Dual pushbutton operation is only available when using the DS1669. The |
| VSD | (3) | PHI | SOP | 2002 | For symmetric signals like C, U, V, Cb, Cr, Pb and Pr, the aver- age DC |
| VSF | (6) | JAT | 1206 | 05+ | The generic processor interface allows the VSF0233F40T to be connected to |
| VSG | (1) | VITESSE | QFP | 04+ | • High-performance, low-cost solution to switch between vid |
| VSI | (13) | SAMPO | 06+ | 12000 | The HYM72V16M736BFU6 Series are Dual In-line Memory Modules suitable for |
| VSK | (8) | div | div | dc81+ | The device is entirely command set compatible with the JEDEC single-powe |
| VSL | (9) | SAMWHA | Active Voltage Programming: Special precautions should be taken when mak | ||
| VSM | (40) | 0805* | 0201+ | 4.6 USB Endpoint 0 Control and Status Register (0xC090: R/W) 4.7 USB Endp | |
| VSN | (3) | SAMWHA | 0402 | 06+ | Factor port regardless of whether the host equipment is operating or |
| VSO | (8) | IC | SOP | Broadcom®, the pulse logo, and Connecting everything® are trademar | |
| VSP | (220) | 200 | BB | 03+ | The information provided herein is believed to be reliable at press time. |
| VSR | (6) | pins 4 & 6 connected See application schematic See application schem | |||
| VSS | (36) | NDK | 08+ | 3. When power is off, current limit input signals on pins 4, 5, 6, | |
| VST | (9) | N/A | PQFP-160 | 99 | Output voltage set internally to 1.5% on SG7800A Input voltage range to 5 |
| VSU | (12) | PANASONIC | 06+ | SOT-23 | Data enable. As defined in the DVI 1.0 specification, the DE signal allow |
| VSW | (1) | 07+ | Pin selectable dividers are used within the PLL and for the output cloc | ||
| VSX | (10) | N/A | The PCF85xxC-2 is a family of floating gate Electrically Erasable Progra | ||
| VT- | (7) | BGA | NVIDIA | 0220+ | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| VT0 | (14) | FAIRCH | SMD | The MCP1726 is a 1A Low Dropout (LDO) linear regulator that provides hi | |
| VT1 | (113) | VOLTERRA | TSSOP | 06+ | The byte pointer bit must be toggled to the correct value before operatin |
| VT2 | (120) | Note 1: Absolute Maximum Ratings are those values beyond which the safety | |||
| VT3 | (50) | egg | egg | dc95 | floppy disk controller is the 82078 core The serial ports are 16550 compa |
| VT4 | (6) | VHK | DIP | The frequency of oscillation of a quartz crystal is determined by its c | |
| VT5 | (26) | FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propa | |||
| VT6 | (104) | TQFP-128 | VIA | 05+ | The HY29DS16x Flash memory array is organized into 39 sectors in two ba |
| VT7 | (29) | DIP | 07+ | DIP | Operation of the circuit is straight-forward. The motor advances |
| VT8 | (208) | VIA | BGA | 0114+ | When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, rel |
| VT9 | (11) | The DS1270 devices execute a read cycle whenever WE (Write Enable) is inac | |||
| VTA | (7) | bel | 0537+ | 7.4.4 NAT: RFC1631, 2663 The Network Address Translator (NAT) implements | |
| VTB | (2) | 铁帽镜 | CAN2 | The HYB39S256400/800/160CT(L) are four bank Synchronous DRAMs organized a | |
| VTC | (49) | VTC | Notes: 1. For max. or min. conditions, use appropriate value specified u | ||
| VTD | (3) | 20/SSOP | 07+/08+ | PROGRAM MEMORY The device contains 4096 bytes of UV erasable or OTP EPR | |
| VTE | (6) | 99 | The PT8000 series is a 60 A high- performance, Integrated Switchin | ||
| VTF | (3) | The codewheel rotates between the emitter and detector, causing the l | |||
| VTG | (1) | VLSI | Select Word 0 (D18 = 0) BitFunction D0Bridge 1 blank time LSB D1Bridge | ||
| VTI | (12) | VTI | QFP208 | O432 | Stresses above the ratings listed below can cause permanent damage to the |
| VTK | (2) | KFIR | QFP2424 | 03+ | Interrupt A, B (three state) - This function is associated with individu |
| VTL | (4) | The IDT70V7519 is a high-speed 256Kx36 (9Mbit) synchronous Bank-S | |||
| VTM | (8) | SOP16M | 2007+ | Features 1) Made of same material as the general purpose chip resi | |
| VTO | (22) | IXYS | MODULE | The DS1270 devices execute a read cycle whenever WE (Write Enable) is inac | |
| VTP | (36) | RYC | 3066 | State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera | |
| VTQ | (3) | IXYS | Module | N/A | Resolution: Accelerometers can be used in a wide variety of low g applica |
| VTR | (3) | hokuriku | hokuriku | dc99 | The ADSP-BF535 processor is a member of the Blackfin processor family of |
| VTS | (15) | VISHAY | TO | DIR input. The enable input G can be used to disable the device so that | |
| VTT | (1) | 06+ | Because the PMOS device behaves as a low-value resistor, the dropout volt | ||
| VTU | (2) | The SMLW010 Single-Output, Low-Profile, PCB Mount Power Modules are low-p | |||
| VTV | (2) | ACRIAN | 2008 | An active high input from an external circuit which latches a Chassis I | |
| VTW | (1) | Most Significant Data Bit (MSB) Data Bits 10C1 Least Significant Data Bi | |||
| VTX | (7) | Four 8-bit registers are provided for control, option select and status m | |||
| VU0 | (66) | Notes 1. Device is considered as a two terminal device: Pins 1,2 3 and 4 | |||
| VU3 | (1) | IXYS | NOTE: The inhibit function of the zero or carry outputs does not end wh | ||
| VU5 | (1) | 07+ | The TLH.42.. series was developed for standard applications like genera | ||
| VU9 | (1) | Purchase of I2C components of Maxim Integrated Products, Inc. or one of i | |||
| VUB | (51) | IXYS | which includes the control and status registers of the on-chip peripher | ||
| VUC | (13) | IXYS | The g-cell plates form two back-to-back capacitors (Figure 3). As | ||
| VUD | (1) | IXYS | 1) for dual channel performance, a minimum of 2 memory modules have to be | ||
| VUE | (10) | Powerful cross-development tools are available from Nation- al Semiconduc | |||
| VUI | (2) | N/A | N/A | N/A | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| VUM | (7) | N/A | The TLC77xxI is characterized for operation over a temperature range of C | ||
| VUO | (337) | IXYS | MODULE | (1) Stresses beyond those listed under absolute maximum ratings may cause | |
| VUS | (1) | Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not pro | |||
| VUW | (1) | JAT | SOT | 04+ | The 16-bit digital output is multiplexed into an 8-bit output word that |
| VV0 | (10) | IXYS | * On products compliant to MIL-PRF-38535, this parameter is not productio | ||
| VV1 | (4) | VISHAY | 3225 | 05+ | ∗ On products compliant to MIL-PRF-38535, this parameter is not pro |
| VV2 | (1) | The crystal or clock frequency chosen must be twice the required process | |||
| VV3 | (2) | SANYO | SOP-24 | 03+ | DESCRIPTION The 74LVX3245 is a dual supply low voltage CMOS OCTAL BUS |
| VV4 | (2) | ||||
| VV5 | (12) | ST | BGA | 00+ | Resetting A low level on the Reset pin (pin 1) resets the interna |
| VV6 | (29) | ST | BGA | N/A | • Easy Gate 1 switch-off with PNP switching transis- tors i |
| VV7 | (1) | 98 | Note 9: Shutdown current is measured in a normal room environment. Exposu | ||
| VVA | (2) | In more severe ambient conditions, the package/junction temperature of | |||
| VVB | (1) | † These characteristics are guaranteed by either production test or | |||
| VVD | (2) | IBM | PGA | 2003 | Configuration data stored in Virtex-II configuration memory can be read |
| VVK | (1) | The bus watcher interfaces to the VVK20U261061/VVK20U261061A/VVK20U261061 | |||
| VVP | (1) | TI | 06-07+ | Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC | |
| VVY | (3) | +5V reference output. This low-drift zener voltage reference is necessary | |||
| VVZ | (36) | PLL1, CLKA, and CLKB each have multiple registers supplying data. Program | |||
| VW- | (2) | The 123NQ... (R) high current Schottky rectifier module series has been o | |||
| VW0 | (1) | 94 | Table 2-0007A/2096V1. One output at a time for a maximum duration | ||
| VW2 | (12) | VWEB | 06+ | The RC4700 also incorporates a two-entry instruction TLB. Each en | |
| VW3 | (8) | 88 | TFK | The set/reset line (SR) is an asynchronous active High con- trol of the | |
| VW4 | (12) | The VPFC input sets the initial full charge reference of the battery pack | |||
| VW5 | (3) | 4 | TFK | The ACE Controller manages FPGA configuration data. The controller prov | |
| VW6 | (1) | VTC | 843 | Popular JEDEC registered 1N5802 to 1N5806 series Voidless | |
| VW8 | (1) | When starting up the circuit utilizing the MSK 4301 for the first time, | |||
| VW9 | (2) | TFK | DIP | 99+ | Thermal Design The IRU1261 incorporates an internal thermal shutdown tha |
| VWB | (1) | MOT | PLCC68 | 07+ | • SMD and through-hole versions with ultra low component hei |
| VWI | (5) | IXYS | Hardware data protection measures include a low VCC detector that automa | ||
| VWM | (1) | IXYS | This document is a general product description and is subject to change wi | ||
| VWO | (8) | IXYS | 04+ | The HYB 39S64400/800/160BT are four bank Synchronous DRAMs organized as | |
| VWS | (8) | N/A | 1Integrated protection functions are designed to prevent IC destruction un | ||
| VWT | (1) | Programmable ground control is useful for internal chip signal managemen | |||
| VX- | (19) | OMRON | 原装 | 08+ | The accumulator closely relates to ALU operations. It is also mapped to l |
| VX0 | (2) | ST | 06+ | 20000 | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga |
| VX1 | (21) | VERSA | QFP208 | 96+ | These three terminal positive regulators are supplied in a hermetically s |
| VX2 | (1) | Four package terminals are used as inputs to set four configuration statu | |||
| VX3 | (17) | N/A | 01+ | TSSOP56 | When V CC falls below 1V, the MAX6806/MAX6808 RESET output no longer sink |
| VX4 | (5) | jauch | jauch | dc95 | • True dual-ported memory cells which allow simultaneous re |
| VX6 | (1) | The MSM7716 is a single-channel CODEC CMOS IC for voice signals that conta | |||
| VX7 | (1) | VXIS | QFP-128P | 02+ | The MIPS integer unit implements a load/store architecture with s |
| VX8 | (12) | hcj | hcj | dc95 | Purchase of I2C components from Maxim Integrated Products, Inc., or one |
| VX9 | (1) | The 0.625C/W assumes the use of the recommended footprint on a gla | |||
| VXA | (5) | HF420: Unsealed,2C, Soldering, Plug-in HF428: Unsealed,2C, PCB HF421: Un | |||
| VXB | (6) | • Excellent Appearance • Slim Font Design • Mitered | |||
| VXC | (2) | The Simultaneous Read/Write architecture provides simultaneous operation | |||
| VXD | (1) | Temperature Sensor diode can be connected, on the board, to any of the AD | |||
| VXE | (3) | in Battery-Powered Applications Like: − Two Battery Cells to 3.3-V | |||
| VXL | (1) | 3. Hitachi makes every attempt to ensure that its products are of high qu | |||
| VXO | (3) | The Erase Suspend/Erase Resume feature allows the host system to pause a | |||
| VXP | (24) | 21 | CAUTION: The BiCMOS inherent to this design of this component increases t | ||
| VXW | (1) | ic-haus | ic-haus | dc0421 | The Functional Block Diagram on Page 1 shows the architecture of the ADSP |
| VXX | (1) | Traditional programmable logic architectures do not implement arithmetic | |||
| VY0 | (100) | 500 | QFP | 02+ | 2.2.1. Specifications, standards, and handbooks. The following spe |
| VY1 | (86) | VLSI | QFP | 07+ | A (sawtooth) reference signal has to be applied to the circuit which can |
| VY2 | (276) | PHILIPS | QFP | 00+ | externally arbitrated or withstand contention when all ports simultaneousl |
| VY3 | (2) | NS | DIP | Changes in field strength at the device face caused by a moving tar | |
| VY5 | (5) | ||||
| VY7 | (1) | 129 | CYPRESS | 96+ | ISB = 2 mA Fully asynchronous and simultaneous read and write ope |
| VY8 | (9) | VLSI | QFP | 00 | • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAM |
| VYA | (1) | The DM9601 provides USB transceiver which is compliant with USB1.1, 10/10 | |||
| VYC | (1) | N/A | CYPRESS | 04+ | addition to the LE and OE pins the AC ACT843 has a Clear (CLR) pin and a |
| VYF | (1) | (•) Pulse width limited by max. junction temperature (r) Include r | |||
| VYI | (1) | The TL750L and TL751L series are low-dropout positive-voltage regulators | |||
| VYO | (1) | • package: colorless, clear 3 mm (T1) package • feature of th | |||
| VYP | (1) | The controller uses a timer to limit fast charge duration. These times ar | |||
| VYR | (25) | vitramon | vitramon | dc82+ | The power dissipation of the SOT-563 is a function of the pad siz |
| VYS | (1) | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |||
| VZ- | (1) | Differential inputs Near zero pop & click 100dB PSRR @ 217Hz with gr | |||
| VZ0 | (6) | N/A | The A-to-B enable (CEAB) input must be low to enter data from A or to o | ||
| VZ1 | (6) | tosh | tosh | dc97 | APPLICATIONS Precision Data Acquisition Systems Battery-Powered Equipme |
| VZ2 | (2) | Unlike traditional OTP digital potentiometers, the VZ200F has a unique t | |||
| VZ3 | (1) | FEATURES ! Drives wide range of n-channel MOSFETs in 3-phase bridges ! | |||
| VZ4 | (1) | The MX98715A features Remote-Power-On and Re- mote-Wake-Up capability a | |||
| VZ5 | (1) | Specifications Outline Dimensions Dimensions of Sensitive Area Positio | |||
| VZI | (1) | PHILIPS | 04+ | The AMC5902 contains a direct PWM control system for spindle and two sl | |
| VZX | (1) | Digital Pixel Inputs These pins accept digital pixel data streams with ei |
About Seekchip- Services - Comments - Contact us - Links - Map
© 2008 China Electronics Market,License 浙ICP备10014259号