| Mfg | pack | D/C | Descrpion | ||
| W.F | (2) | Preliminary product information describes products which are in productio | |||
| W/B | (1) | ||||
| W/F | (1) | ||||
| W/H | (1) | ||||
| W/S | (1) | ||||
| W/W | (1) | ||||
| W0- | (1) | For the most current package and ordering information, see the Package Op | |||
| W00 | (9) | GENERAL INSTRUMENT | 87+ | Burst mode operation Auto & self refresh capability (8 | |
| W01 | (17) | SILICONIX | 1650 | RESET: This active low input causes a chip reset which lasts for 26 clock | |
| W02 | (10) | The safe operating area curves indicate ICCVCE limits of the tran | |||
| W03 | (5) | XEROX | DIP8 | The DP8417 8418 8419 8419X represent a family of 256k DRAM Controller Dr | |
| W04 | (19) | ST | SOP-8 | The device has two supply voltages. VCC is designed for 3-V to 3.6-V ope | |
| W05 | (4) | N/A | 01+ | SOP-8 | The preamble (Figure 9 on page 10) with up to 320 periods of the 125 kHz |
| W06 | (15) | SEP | 2008+ | NOTES: 1. Dimensions are in inches. 2. Metric equivalents ar | |
| W07 | (3) | TOSHIBA | 06+ | 9200 | Time Out Counter. The Time Out is performed by a 14 Bit Counter that co |
| W08 | (11) | SONY | 2001 | The W0889-1A is a Stealth™ diode optimized for low loss performanc | |
| W09 | (1) | †Purchase of I2C components from Maxim Integrated Products, Inc. or | |||
| W0A | (15) | Information in this document is provided in connection with Intel ® p | |||
| W-1 | (4) | N/A | N/A | N/A | The Am29LV652D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supp |
| W1- | (4) | TOSHIBA | SOT-23 | 04+ | SM6610 series is high-accuracy temperature sensor IC in the ultra small p |
| W10 | (24) | Hitachi | 98 | Input Undervoltage Lockout (UVLO) The MAX5069A EV kit features a | |
| W11 | (21) | ST | TO-247 | The designer can create, implement, and verify digital logic circuits fo | |
| W12 | (40) | NATIONAL | 2008 | Conexant products are not intended for use in medical, life saving or lif | |
| W13 | (54) | 2 | When expander logic is used in the data path, add the appro- priate maxim | ||
| W14 | (33) | WIN | DIP | 99 | Providing two banks of four outputs, the PI6C2308A is a 3.3V zero- delay |
| W15 | (51) | TI | 4000 | 00+ | Only few external Components required Input Undervoltage Lockout 67kHz |
| W16 | (33) | 96 | The MX98715A controller is an IEEE802.3u compliant single chip 32-bit f | ||
| W17 | (48) | CYPRESS | SOP8 | 01+/05+ | The device is enabled when EN is set from logic low to logic high. CP1 wi |
| W18 | (76) | CYPRESS | 03+ | 2.1 W/Ch Into 4 Ω at 5 V • 1.4 W/Ch Into 8 Ω at 5 V | |
| W19 | (40) | CY | 03+/P1 | SOP/28 | The threshold value is established as an offset to the reference level. |
| W1A | (11) | N/A | Microstrip Series Connection for HSMP-482x Series In order to take full | ||
| W1B | (1) | • The W1BA supports programmable PCI Subsystem ID and Subsy | |||
| W1D | (1) | ST | 2008 | • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillato | |
| W1G | (1) | The W1G-IC766708 has CMOS standby mode which re- duces the maximum VCC cu | |||
| W1O | (1) | PARAMETER Error Comparator Section Input Bias Current Input Offset Volt | |||
| W1S | (1) | Features O 5V tolerant inputs and outputs O 2.3VC3.6V VCC specifications | |||
| W1X | (1) | vishay | vishay | dc02 | High voltage semiconductor especially designed for horizontal deflectio |
| W-2 | (3) | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |||
| W2- | (7) | 十脚铁帽 | 08+ | The output power as a function of the supply voltage is measured on the o | |
| W20 | (73) | LUCENT | LUCENT | 00+ | Functional Description Analog Front-End Input Selector Clamping Automa |
| W21 | (87) | UNI | Note 1: All parameters specified over standard operating conditions unles | ||
| W22 | (72) | The LM393 series are dual independent precision voltage comparator | |||
| W23 | (58) | CYP | SSOP48 | 0118+ | Input voltage range: 2.25V to 5.5V Ultra-low IQ: Only 16&m |
| W24 | (350) | WINBOND | PLCC | 98+ | At both ends of the array and between each resistor segment is a CMOS s |
| W25 | (104) | WINBOND | 04+ | 2. Data labelled Typ is not to be used for design purposes but is intende | |
| W26 | (33) | CYPRESS | O7+ | 1. MC100ES6139 circuits are designed to meet the DC specifications shown | |
| W27 | (133) | Windond | PLCC32 | 03/+04+ | /RCS0 -->/CS : SDRAMs D0-D8 /RCS1 -->/CS : SDRAMs D9 - D17 RBA0-RB |
| W28 | (35) | WORKS | The UCC3808 dual output drive stages are arranged in a push-pull configur | ||
| W29 | (170) | AT | PLCC | The VSP2232 is a complete mixed-signal IC that contains all of the key fe | |
| W2A | (21) | AVX | 2005(PF) | Turn-On Time: In the circuit of Figure 1, turning Q1 on applies a low vol | |
| W2B | (2) | 铁面BGA | Feedback Voltage and Short Circuit Detection pin. It is the inverting inp | ||
| W2C | (3) | MOTOROLA | Low voltage noise density of 2.1nV/Hz and -88dBc spurious-free dynamic ra | ||
| W2D | (1) | AVX | 0805电容 | 02+ | The LIN driver function LIN_IdleClock can check whether or not there is a |
| W2E | (3) | For reasons of interference protection and surge immunity, the supply vol | |||
| W2F | (10) | AVX | 0805-100P | 05+ | s No products described or contained herein are intended for use in surgi |
| W2G | (7) | ST | 98 | TAOperating free-air temperature−55125−4085C NOTE 3: A | |
| W2J | (1) | The Clock oscillator may be stopped at any time. To increase the shelf li | |||
| W2L | (6) | AVX | 0402X4 | Vcc = 2.3V~2.7V, TA= 0C to 70C/ -40C to 85C, unless otherwise specified & | |
| W2M | (1) | DC bus capacitor filter with NTC inrush current limiter IR | |||
| W2N | (2) | HARRIS | DIP4 | CP: This is the input for the charge pump. For applications requiring a c | |
| W2O | (1) | SOP8 | 5. ML66Q525B with flash memory programmable with single power supply &nbs | ||
| W2R | (1) | OMRON | MODEL | 00+ | Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level |
| W2S | (1) | Specifications contained in this product brief are in effect as of the pu | |||
| W-3 | (5) | IR | MODULE | The addition of software reset enables recovery from unforeseen error co | |
| W3- | (2) | TOSHIBA | SOT-23 | 05+ | The DS1481 also supports overdrive communication with overdrive capable |
| W30 | (31) | LUCENT | TSSOP | 1999 | Notes 1. All voltages referenced to Vss. 2. An initial pause of 100 &m |
| W31 | (36) | CYPRESS | SSOP-48 | 00+ | State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Opera |
| W32 | (31) | cyp | 03+ | The MAX6950 and MAX6951 were intended to drive single-digit displays, and | |
| W33 | (12) | WINBOND | N/A | 99+ | The MAX1737 evaluation kit (EV kit) is an assembled and tested PC board t |
| W34 | (7) | WORKS | 98/93 | SOP-8 | Thermal Design The IRU1015 incorporates an internal thermal shutdown tha |
| W35 | (8) | N/A | N/A | N/A | NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow |
| W36 | (1) | The REG103 is a family of low-noise, low-dropout, linear regulators with | |||
| W37 | (2) | ST | 04+ | • TOSHIBA is continually working to improve the quality and reliabil | |
| W38 | (13) | WINBOND | PLCC-28 | To further understand 82C37A operation, the states generated by each cl | |
| W39 | (78) | WINBIND | PLCC32 | 06+ | External I/O for Timer/Counter 2 Timer/Counter 2 Capture/Reload Trigger |
| W3A | (46) | N/A | Stresses beyond those listed in the Absolute Maximum Ratings may cause pe | ||
| W3B | (1) | TI | QFN | 07+ | The Intersil ICL7106 and ICL7107 are high performance, low power, 31/2 d |
| W3F | (12) | N/A | 1206 | ||
| W3H | (1) | In order to take advantageof the 4 point structure of the LCP, the TIP | |||
| W3L | (4) | AVX | 2007+PB | Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply | |
| W4- | (3) | TOSHIBA | SOT-23 | © Cypress Semiconductor Corporation, 2004. The information contained | |
| W40 | (70) | MOT | 05+ | Following the address and acknowledge bit with logic 0 in the read/write | |
| W41 | (5) | ICWORKS | SSOP/48 | 99+ | The intended application of this device and signaling technique is for po |
| W42 | (106) | BGA | ATI | 250 | The ISP1161A is a single-chip Universal Serial Bus (USB) Host Controller |
| W43 | (11) | WINBOND | DIP | 95 | The attached datasheets are provided by ICSI. Integrated Circuit Solution |
| W45 | (3) | N/A | ICWORKS | 04+ | Auxiliary receive filter output. The output signal is inverted with respe |
| W46 | (1) | Some of the topologys advantages are: 1) Stepping up or down the input vo | |||
| W47 | (1) | MLP-S16P | 38503 | N/A | The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex Bu |
| W48 | (242) | N/A | ICWORKS | 04+ | PCI Bus VIO: This pin should be connected to the VIO pins of the PCI bus. |
| W49 | (82) | N/A | ICWORK | 04+ | This unit controls all operations on addresses (calculates the next instru |
| W4B | (1) | NTT DaTa | High speed output rise and fall (20 ns typ) at load capacitance (CL) of | ||
| W4C | (2) | NTT DaTa | 98 | In addition to the H-LUT input control multiplexers (shown in box " | |
| W4N | (1) | N/A | N/A | N/A | The Start Circuitry generates the internal START signal which causes th |
| W4T | (1) | 01+ | SOP | This document is a general product description and is subject to change wi | |
| W-5 | (1) | † Design targets only. Not tested in production.. NOTES: 5. Both | |||
| W50 | (7) | N/A | DIP | 01+ | • Photo detector and preamplifier in one package • Internal |
| W51 | (18) | WIZNET | 08+ | C Internal Address and Data Latches for 128 Bytes C Intern | |
| W52 | (29) | WIN | 1999 | DIP | Electrical These devices use a modified 4 x 7 dot matrix light emittin |
| W53 | (14) | Multiformat video decoder supports NTSC-(M, N, 4.43), PAL-(B/D/G/ | |||
| W54 | (15) | 3956 | WIN | 03+ | Notes: 3. These specifications are guaranteed only for the test conditio |
| W55 | (18) | WINBOND | 2007 | The basic unit of logic on the ispLSI 3160 device is the Twin Generic L | |
| W56 | (13) | WINBOND | PLCC-28 | The MSK 5115 series are highly thermally conductive devices and the ther | |
| W57 | (20) | WINBOND | SSOP | 02+ | IF+, IF C (Pins 2, 3): Differential IF Signal Inputs. A differ- ential si |
| W58 | (35) | WINBOND | . | 10 | Terminal nos. 3 and 8 are soft start terminals. Connect a capacitor to th |
| W59 | (3) | NTT DaTa | 98 | Extended data out (EDO) allows data output rates up to 40 MHz for 60-ns d | |
| W5B | (1) | NS | SOP-14 | SX | Notes: 1. See test circuit and waveforms. 2. This parameter is guarant |
| W5L | (1) | 17 | ST | 00+ | VID0-4 are the input pins to the 5-bit DAC. The states of these five pins |
| W5N | (2) | Specifications are not production tested but guaranteed by design | |||
| W5P | (1) | Host clock frequency selection is achieved by applying the appropriate lo | |||
| W5Q | (1) | On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external so | |||
| W6- | (1) | NEC | SOT23 | 01+ | Only the destination of the lower-order byte in the ta- ble is well-defin |
| W60 | (5) | 95 | SUMMARY High-Performance 32-Bit DSPApplications in Audio, Medica | ||
| W61 | (1) | N/A | NEW | 95+ | Output drive power down C An active low signal that controls the power-do |
| W62 | (12) | With an increasing supply voltage the IC enters the start-up state; the | |||
| W63 | (3) | BI | SOP-8 | 99/P3 | IDTCV104B is a 48 pin clock generation device for desktop PC platf |
| W64 | (5) | WINBOND | LCC | Inhibit: The Inhibit pin is an open-collector/drain negative logic input | |
| W65 | (20) | 04+ | 3.4.1 Lead finish and formation. Lead finish shall be solderable i | ||
| W66 | (13) | WINBOND | 99 | The MSP430x11x2 and MSP430x12x2 series are ultralow-power mixed signal mi | |
| W67 | (15) | N/A | 06+ | 496 | Referenced to VCCA Voltage VCC Isolation Feature − If Either VCC In |
| W68 | (45) | Remote On/Off: This is an open-collector (open-drain) negative logic inpu | |||
| W69 | (6) | CHIPS | BGA | 97+ | • Protects Sensitive circuits from short duration fast rise |
| W6N | (5) | ST | INPUT OFFSET VOLTAGE, initial4 OFFSET VOLTAGE, vs. temperature4 OFFSE | ||
| W7- | (5) | TOSHIBA | SOT-23 | 05+ | The device supports low-power standby operation. When RESET is low, the d |
| W70 | (6) | WACOM | 00+ | TQFP-M100P | " Window structured high power laser diode ideal for high speed &nb |
| W71 | (4) | DESCRIPTION The STi7710 is STMicroelectronics first single chip set-top | |||
| W72 | (4) | TI | DIP | These N-Channel enhancement mode power field effect transistors are produ | |
| W73 | (11) | SI | SOP-8 | N/A | This pin normally functions as a three-state input that controls the two |
| W74 | (30) | W | 03+ | SMD | TheSN55LVDS32,SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are differenti |
| W75 | (4) | Winbond | The device also includes a 1 volt regulator capable of sourcing u | ||
| W76 | (7) | COILCRAFT | 128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, | ||
| W77 | (111) | Winbond | 7+ | The MSK 4351 is a 50 Amp, 3 Phase Isolated Bridge Smart Power Moto | |
| W78 | (451) | N/A | WINBOND | 04+ | Zero dead time switching Maximum output current 7.5 A Standby mode Hi |
| W79 | (61) | Winbond | PLCC | 06+ | † Stresses beyond those listed under absolute maximum ratings may c |
| W7B | (1) | NS | SOP-14 | SX | The Transmit section input, VFXI, is a high impedance sum- ming input w |
| W7L | (1) | 07+ | tPLDhOutput enable time3⋅T + tPD4⋅T + tPDnsT=CLK period &nbs | ||
| W7N | (5) | N | 96+ | TO-220 | † Stresses beyond those listed under absolute maximum ratings may c |
| W7P | (4) | Sector Read With sector read, a sector address is supplied with the rea | |||
| W8- | (6) | TOSHIBA | SOT-143 | The EVBD4400 evaluation board implements a single power phaseleg circui | |
| W8/ | (1) | System Resources, some of which have been previously listed, provide add | |||
| W80 | (15) | 05/06+ | Sensitivity describes the gain of the sensor and can be determined by app | ||
| W81 | (17) | 93 | This MOSFET is an enhancement-mode silicon-gate power field effect | ||
| W82 | (46) | 03+ | The RESET pin is asserted whenever VCC falls below the reset threshold v | ||
| W83 | (329) | Winbond | 08+ | FEATURES High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over | |
| W84 | (2) | 98 | Input. This input is not considered active unless it is active for at lea | ||
| W85 | (4) | WINBOND | SOP/24 | 90+ | The FETKY™ family of Co-Pack HEXFET® Power MOSFETs and Schottky |
| W86 | (27) | WINBOND | PLCC-68 | 04+ | The Spartan™ and the Spartan-XL families are a high-vol- ume produ |
| W87 | (6) | WINBOND | QFP | 06+ | All devices also available in tray quatities. For the most current |
| W88 | (40) | Winbond | QFP | 1997 | Description The HSDL-3612 is a low-profile infrared transceiver module |
| W89 | (29) | WIN | QFP | 1995 | 1/0 Read the contents of the Wiper Counter Register pointed to by |
| W8B | (1) | NS | SOP-14 | SX | Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a |
| W8F | (1) | The device contains two operational amplifiers and a precision shunt re | |||
| W8N | (5) | N/A | • NPT IGBT technology - high switching speed - low | ||
| W-9 | (2) | TI | A and B Ports Up To −2 V Integrated Diode to VCC Provides 5-V Input | ||
| W9- | (4) | TOSH | SOT-23 | 05+ | An internal oscillator fixes the switching frequency at 500KHz to minim |
| W9/ | (1) | The MTC20136 is a dedicated controller chip, spe- cifically designed to | |||
| W90 | (13) | LUCENT | QFP32 | PB0~PB5 constitute a 6-bit Schmitt trigger input port. Each bit on port ar | |
| W91 | (216) | WINBOND | . | 1000 | The FCT573Tis an octal transparent latch built using an advanced d |
| W92 | (28) | ST | TO263 | 02+ | Unless otherwise specified, these specifications apply at an ambient oper |
| W93 | (35) | N/A | SMD | 04+ | preamplifier. An external microphone should be AC coupled to this pin via |
| W94 | (22) | QFP | The W941232AD-5 supports GMII, RGMII, SGMII, SerDes, TBI, RTBI, and MII | ||
| W95 | (2) | A ceramic capacitor(0.1µF) should be connected from pin 8 to pin 5 t | |||
| W96 | (1) | The major functional blocks of the PSD3XX include: • Two pr | |||
| W97 | (5) | 07+ | The HC534, HCT534, HC564, and HCT564 are positive edge triggered flip-f | ||
| W98 | (133) | WINBOND | TSOP | Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arit | |
| W99 | (87) | N/A | PLCC44 | N/A | Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile) The Block Protect Bit |
| W9A | (1) | Operating the two memory banks in an interleaved fashion allows random ac | |||
| W9B | (1) | NS | SOP-14 | SX | Skyworks APD Series of silicon PIN diode chips are designed for use as sw |
| W9C | (2) | Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a | |||
| W9D | (1) | A buffered output-enable (OE) input can be used to place the eight output | |||
| W9E | (1) | The TC55V8512JI/FTI is a 4,194,304-bit high-speed static random ac | |||
| W9G | (2) | Max. UnitsConditions CCCVVGS = 0V, ID = 250µA CCCV/C Refere | |||
| W9M | (1) | BENEFITS • Long life • Maintenance free • Current-lim | |||
| W9N | (6) | ST | TO-220F | Information furnished by Analog Devices is believed to be accurate and r | |
| WA- | (1) | Notes: 4. CX1 must be placed within 0.7 cm of the HSDL-3612 to obtain op | |||
| WA0 | (21) | APEX | CAN8 | 08+ | The choice of C2 is a compromise between an accept- able startup |
| WA1 | (15) | UJ | TQFP | 02+ | The output current which can be drawn from the comparator reference (Ire |
| WA2 | (9) | N/A | N/A | N/A | The AD8353 can also operate with a 5 V power supply, in which case no ex |
| WA3 | (5) | N/A | N/A | N/A | Reading from the device is accomplished by taking Chip En- able (CE) an |
| WA4 | (4) | YAMAHA | SOP24W | 2007+ | This is not an extensive capacitor list. Capacitors from other vendors a |
| WA5 | (3) | 2. Force IDL Transmit This enhancement is an additional SCP cont | |||
| WA6 | (8) | 55 | MODULE | Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Ope | |
| WA7 | (2) | Small 10-Lead MSOP or DFN Package Uses Tiny Capacitors and Inductor High | |||
| WA8 | (9) | WLW | AXIAL | 5 | High location function normally (see Figure 5). If bit 2 is 1, the assoc |
| WA9 | (2) | QFP | 03+/04+ | The Fairchild Switch FST16209 provides 18-bits of high- speed CMOS TTL- | |
| WAB | (9) | IR | 421B | SMD220-5 | 3-wire serial digital data link requires few I/O pins Analog input trac |
| WAC | (36) | 07+ | High current sink/source 25 mA/25 mA Up to 76 I/O with individual direc | ||
| WAE | (3) | SMT | 00+ | • For indirect jumps and calls that use a 16-bit DAG address | |
| WAF | (19) | ST | BGA | 99 | Hynix HYMD132G725A(L)8-K/H/L series is registered 184-pin double data rate |
| WAG | (3) | LSILOGIC | BGA | 04+ | Figure 1 shows the basic architecture of the STA111. The devices major f |
| WAH | (3) | SOP48 | 06+ | The IGBT is ideal for many high voltage switching applications operating | |
| WAL | (3) | Read operations are initiated in the same way as write operations with th | |||
| WAM | (3) | The MAX2531 multiband LNA/Mixer IC is optimized for CDMA, GSM, and | |||
| WAP | (1) | WAVECOM | BGA | Edition 07.96 This edition was realized using the software system FrameMa | |
| WAR | (15) | PHILIPH | QFP | 04+ | Guaranteed monotonic INL error: 1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/C |
| WAS | (10) | N/A | ATMEL | 04+ | The device is available with an access time of 70, 90, or 120 ns. The d |
| WAT | (7) | ST | 05+ | SOP-20 | The UCC28510 family also features leading-edge modulation for the PFC sta |
| WAV | (2) | During interrupts and subroutine calls, the return address program counte | |||
| WB- | (6) | N/A | 1812 | GND (Pin 10): Signal Ground. The oscillator, slew control circuitry and t | |
| WB0 | (4) | TSOP8S | 2007+ | NOTE: 1. Because the gate controls are asynchronous, runt pulses are pos | |
| WB1 | (58) | MN662790RSC is a signal processing LSI for CDs which is applicable to 4x- | |||
| WB2 | (20) | SINCERA | 0805-70R | 05+ | A serial communications interface (SCI) is integrated on all devices to p |
| WB3 | (30) | COILCRAFT | The following specifications apply for AGND = DGND = DGND(I/O) = 0V, VA = | ||
| WB4 | (6) | N/A | 1812 | If you have any questions or comments regarding this publication, please | |
| WB5 | (2) | N/A | DIP | 98 | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (t |
| WB6 | (6) | ZIOLG | QFP | DESCRIPTION The CLP30-200B1 is designed to protect telecommunication e | |
| WB8 | (5) | WB | SOP-8 | N/A | The HT24LC08 is an 8K-bit serial read/write non-volatile memory device us |
| WBA | (2) | JAT | 4(0603) | The MAX1533/MAX1537 are dual step-down, switch- mode power-supply (SMPS) | |
| WBC | (7) | pny | pny | dc00 | (1) All typical values are at TA = +25C. (2) Integral nonlinearity is d |
| WBD | (1) | The ground return for the digital supply for the ADC12DL065s output driv | |||
| WBH | (1) | TI | TSSOP48 | 06+ | The variable product-term distribution on this device removes rigid limit |
| WBL | (5) | Cortina | 07+ | Over Voltage Detection The MX841 will go into a shutdown state to avoid | |
| WBR | (6) | Information in this document is provided in connection with Intel product | |||
| WBS | (1) | The following addresses are reserved for special purpose : $FFFAh | |||
| WBT | (1) | N/A | Boomer audio power amplifiers were designed specifically to provide hig | ||
| WBU | (2) | ||||
| WC0 | (4) | HIT | The FM1233A permits a pushbutton (or a signal) to initiate a reset exter | ||
| WC1 | (3) | MOT | CDIP | 90+ | The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_ |
| WC2 | (1) | PIN and NIN should be differentially driven, ac-coupled for optimu | |||
| WC3 | (3) | WDC | PLCC | A read cycle is initiated by the falling edge of CAS or OE, whichever o | |
| WC4 | (3) | SENOR | 1206-470K | 05+ | DC ACCURACY Integral Linearity Error Differential Linearity Error No |
| WC5 | (1) | This device has been designed to meet the increasing demand for white S | |||
| WC6 | (3) | WDC | 12018 | 01+ | 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access |
| WC7 | (1) | wdc | wdc | dc92 | Reading from the device is accomplished by taking Chip En- able 1 (CE1) |
| WC8 | (3) | The internally switched supply voltage, VINT (ei- ther VCC input or VBAT | |||
| WCA | (4) | READ OPERATIONS Read operations are initiated in the same way as write op | |||
| WCC | (2) | reset (pin 4) An active low input that forces both outputs low, | |||
| WCD | (1) | I/ODescription Data inputs for an 18-bit bus. When RS is se | |||
| WCE | (3) | Notes: 7. The luminous intensity, I V, is measured at the peak of the sp | |||
| WCF | (4) | The 33099 is designed to regulate the output voltage in diode-rect | |||
| WCG | (3) | HYUPJIN | !Features 1) Built-in bias resistors enable the configuration of an &nbs | ||
| WCI | (21) | N/A | 3225 | • Fast Page Mode Access Cycle • TTL compatible inputs and out | |
| WCL | (3) | AMIS | 07+ | The device is entirely command set compatible with the JEDEC single-powe | |
| WCM | (57) | TAI-TECH | SMD | 07+ | Now we can examine the value of < f, ( C ä) >. < f, ä |
| WCO | (1) | ||||
| WCP | (1) | Item Repetitive Peak Off-State Voltage R.M.S. On-State Current | |||
| WCR | (381) | welwyn | welwyn | dc06 | • Precision voltage monitor for 3V, 3.3V or 5V power suppli |
| WCS | (12) | DALE | 晶振 | 2000 | After initialization and synchronization, the serializer accepts parallel |
| WCT | (5) | 8 | DESCRIPTION These dual channel diode-transistor optocouple | ||
| WCW | (2) | Panasonic | 1812-223 | 05+ | tpLZ7nsDisable time, low-level-to-high-impedance output (1) All t |
| WD- | (11) | JAE | The HEF4094B is an 8-stage serial shift register having a storage latch | ||
| WD1 | (246) | WDC | DIP | 04+ | The MCP6295s VCM for op amp B (pins VOUTA/VINB+ and VINBC) is VSS + 100 m |
| WD2 | (62) | WDC | DIP | 84 | This pin is IF input to double balanced mixer (DBM). The input is desig |
| WD3 | (83) | 07+ | If the instruction preceding the REF has a redundancy effect, this effect | ||
| WD4 | (16) | WDC | O7+ | After power-on-reset, the ATA5275 is in standby mode. For minimum power c | |
| WD5 | (22) | Notes: 1. See test circuit and waveforms. 2. This parameter is guarantee | |||
| WD6 | (66) | SUMMIT | DIP/8 | 94+ | Programmable window comparators monitor Over-Voltage (OV) and Under-Volt |
| WD7 | (74) | N/A | WDC | 04+ | Maximum / minimum signal levels The following table gives the transmitte |
| WD8 | (50) | WD | CDIP40 | —— | Operating features include an on/off inhibit, output voltage adjus |
| WD9 | (98) | WDC | QFP | 94+ | Supports a 33-MHz, 64-bit PCI host bus interface with a 264 MB/sec maxim |
| WDC | (28) | The HY628400A is a high-speed, low power and 4M bits CMOS SRAM organized | |||
| WDD | (8) | VOUT Temperature Coefficient DC Crosstalk2 REFERENCE INPUT | |||
| WDE | (1) | To measure a refractive index, the LED must be illuminated during the mea | |||
| WDG | (4) | CAN10 | Eight (388) or Sixteen (386) Line Receivers Meet or Exceed the Requiremen | ||
| WDI | (2) | The S3C72N8/C72N5 microcontroller is also available in OTP (One Time Progr | |||
| WDK | (8) | Enable/Undervoltage Lockout (Input): A low level on this pin will power d | |||
| WDL | (3) | WDL | DIP | 1990 | TAOperating free-air temperatureC55125C4085C NOTE 3: All unused in |
| WDM | (8) | MP3 Decoding Functions (MPEG audio standard [ISO/IEC 11172-3] layer 3) | |||
| WDO | (2) | MOT | SOP-16 | 00+01+ | AVDD Operating CurrentIAVDDVAVDD = 20V20µA Note 1: Limits are |
| WDP | (1) | Aluminum electrolytic or tantalum capacitor types can be used. (Because | |||
| WDR | (2) | HERMATEK | TSSOP | 0311+ | KEY1~KEY8 all function as trigger keys. By mask option, the HT812L0 provi |
| WDS | (1) | bosch | bosch | dc97 | They provide transparent enhancements to Intels 8xC251Sx family with an a |
| WDT | (1) | ics | ics | dc03 | HEXFRED diodes are optimized to reduce losses and EMI/RFI in high frequen |
| WDV | (1) | The EEPROM has a capacity of 256 bits and is organized in 8 pages of 4 | |||
| WDW | (1) | ic-haus | ic-haus | dc03 | The HSDL-3612 can be completely shut down to achieve very low power c |
| WDX | (1) | The FSTD3306 is a 2-bit ultra high-speed CMOS FET bus switch with enhan | |||
| WDY | (1) | WDY | 04+ | SIP | 2.1 Transmit-only mode The device will power up in the transmit-only mode |
| WE- | (3) | LUCENST | 9711 | On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive In-System D | |
| WE/ | (3) | AC characteristics are guaranteed by design and characterization. PWC = ( | |||
| WE0 | (4) | TSOP8S | 2007+ | Isolated Hermetic Package, JEDEC TO-257AA Outline Reference Voltages Se | |
| WE1 | (26) | AT&T | . | 9 | Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/R |
| WE2 | (29) | LUCENT | 4.4.2 Group B inspection. Group B inspection shall be conducted in | ||
| WE3 | (33) | stock | Halt function and wake-up feature reduce power consumption Up to 0.5ms | ||
| WE4 | (7) | DIP8 | 2007+ | The following characteristics are applicable to the operating temperature | |
| WE5 | (2) | ST | SMD | 98+ | Low input current with normal VCC or VCC e 0V (30 mA typ) High noise imm |
| WE6 | (16) | N/A | N/A | N/A | To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the |
| WE7 | (2) | gain, one of two (or both) Cz capacitors can be switched to subtract cha | |||
| WE8 | (5) | TOKO | 04+ | SMD | The ISR functions normally with pin 1 open-circuit, providing a regulate |
| WE9 | (34) | WIN | DIP | 89+ | The HYS 64V4300 is an industry standard 168-pin 8-byte Dual in-line Memor |
| WEB | (3) | MOT | PLCC52 | 06+ | removal of EEPROM devices. DMS will also allow the system software to b |
| WED | (38) | DIP | Notes: 1. The voltage on any input or I/O pin cannot exceed the po | ||
| WEE | (2) | IC | SOP | Note 1: In the typical PECL 100K logic output Voh is 2.35 volts and Vol | |
| WEF | (3) | AT&T | . | 32 | The AWT6135 meets the increasing demands for higher efficiency and line |
| WEL | (10) | The current-control circuitry limits the load current as follows: | |||
| WEN | (1) | ST | 07+ | (2) Storage The BG-LEDs should be stored at 30C or less and 70%RH | |
| WEQ | (3) | These very small, low cost filters are intended for use with A-D and D-A | |||
| WER | (3) | Panasonic | Transmit Input. Balanced differential line receiver inputs to the Transmi | ||
| WES | (1) | The UPC2753GR is a frequency converter manufactured with the NESAT III | |||
| WF- | (1) | N/A | 0603L | It is important that the logic used to turn ON and OFF the various transi | |
| WF0 | (8) | ST | 01+ | Maximum ratings are those values beyond which device damage can occ | |
| WF1 | (16) | N/A | 04+ | NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are | |
| WF2 | (8) | stock | ¡In the absence of confirmation by device specification shee | ||
| WF3 | (5) | NEC | Light has characteristics to move electrons in the integrated circuitry of | ||
| WF4 | (5) | NEC | 01+ | NOTES: 1. Stresses beyond those listed may cause permanent damage to the | |
| WF5 | (7) | NEC | FEATURES High Ripple Rejection75dB typ. (f=1kHz Vo=3V Version) & | ||
| WF6 | (16) | JAT | • Hot-swapping and hot-docking (low resistance for PCI and | ||
| WF7 | (31) | ST | 07+ | Input Channels 0-3 PECL/ECL differential signal inputs. Multiplexing of t | |
| WF8 | (3) | NRS | 03+ | This access is initiated when the following conditions are satisfied at c | |
| WF9 | (10) | 92 | DIP | Reading from the device is accomplished by taking Chip Enable (CE) and Ou | |
| WFA | (4) | 95 | The user can program the frequency of the output banks through nF[0:1] an | ||
| WFB | (1) | 2. Products and product specifications may be subject to change without n | |||
| WFC | (5) | AMIS | 07+ | The TC58FVT160/B160A is a 16,777,216-bit, 3.0-V read-only electric | |
| WFD | (9) | ST | 07+ | 918 | The 34-pin PowerCap module integrates SRAM memory and NV control along wit |
| WFF | (9) | ISDOM | TO220 | 2007+ | The HYB 39S256400/800/160T are four bank Synchronous DRAMs organized as |
| WFH | (1) | Typical represent average readings at 25C, VDD = 5 V. Re | |||
| WFI | (2) | WFI | DIP | DIP | Note 1: Absolute Maximum Ratings are those values beyond which the safety |
| WFK | (1) | 2. Using a CAS-before-RAS refresh cycle. CAS-before- RAS refresh | |||
| WFM | (1) | • High speed tAA = 10ns • Low active power for 10 ns | |||
| WFP | (12) | 06+ | QFP | The EM78860 is an 8-bit RISC type microprocessor with low power , high sp | |
| WFR | (3) | N/A | NSC | 04+ | Note 3: Minimum load current is defined as the mini- mum current required |
| WFS | (1) | C Asynchronous Access Time C 70 ns C Page Mode Read Time C | |||
| WFU | (2) | TO-251 | 06+ | -331.40 -194.50 -48.00 87.40 235.20 383.40 530.40 | |
| WFW | (1) | 1) CPD is defined as the value of the ICs internal equivalent capacitance | |||
| WFX | (6) | JAT | 2520 | 05+ | In order to compensate for the loss of the high-frequency signal componen |
| WFZ | (1) | N/A | DIP | 1991 | These pins should each be bypassed to AGND with a low ESL (equivalent s |
| WG0 | (5) | N/A | 06+ | 500 | Note: Hitachis serial EEPROM are authorized for using consumer applicatio |
| WG1 | (3) | BICDC | DIP | 2002 | Note 11: If the product is in shutdown mode and VDD exceeds 6V (to a max |
| WG2 | (1) | Collector-to-Emitter Voltage Continuous Collector Current Continuous | |||
| WG3 | (1) | netgear | netgear | dc 06+ | • wideband coverage, DC to 18 GHz • extra rugged constructi |
| WG4 | (1) | A/D & D/A converters: which are implemented with 2nd-order sigma-de | |||
| WG6 | (2) | Jack(Available) | Functional improvements have also been implemented in this family. The U | ||
| WG7 | (1) | DELAB, DELCD: Delay Programming Between Complementary Outputs. DELAB pro | |||
| WG8 | (5) | INTEL | 06+ | Generates 106.25 MHz clocks from a 21.25 MHz crystal Less than 45ps one | |
| WG9 | (1) | 03+ | The EB1175 evaluation board is available to aid designers in demonstrati | ||
| WGA | (2) | The HIP6017 provides the power control and protection for three output | |||
| WGC | (1) | ||||
| WGJ | (2) | The HEDS-5500, 5540, 5600, 5640, and the HEDM-5500, 5600 provide moti | |||
| WGM | (1) | The CS4344 family members are complete, stereo digital-to-analog output s | |||
| WGP | (4) | This publication is issued to provide information only and (unless agreed | |||
| WGR | (1) | Intel | board, minimum creepage and clearance requirements must be met as specif | ||
| WGS | (2) | • JEDEC registered 1N5333 to 1N5388B • Zener voltage availa | |||
| WGU | (1) | ||||
| WGW | (1) | SUPPLY VOLTAGE C VCC = 3V to 3.6V for Program, Erase and Read Op | |||
| W-H | (1) | ||||
| WH- | (1) | N/A | DIP18 | 03+ | The DMA controller is a state-driven address and control signal generato |
| WH0 | (2) | N /A | 00+ | N/A | Current versions of the MC68HC908AZ60A data sheet specify a maximum tota |
| WH1 | (21) | N/A | N/A | N/A | The four manuals listed in Table 1 are required for a complete descript |
| WH2 | (34) | HAIER | DIP42 | * 3.5 Marking. Devices shall be marked in accordance with MIL-PRF-19500, | |
| WH3 | (3) | N /A | 00+ | N/A | 8-bit Resolution 500 Msps (min) Sampling Rate Power Consumption: 3.8W Ty |
| WH4 | (3) | N/A | NOTES 1See the Terminology section. 2Temperature range (A, B Version): C | ||
| WH5 | (14) | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch | |||
| WH6 | (1) | This is a stress rating only and functional operation of the device at the | |||
| WH8 | (1) | XC4000E devices have generous routing resources to accommodate the most | |||
| WH9 | (1) | The WH91BA06W11H provides the receiver functions of quantization, signal | |||
| WHA | (2) | 裸片 | 00+ | • Automatic power-down • Expandable data bus to 32/36 bits or | |
| WHB | (1) | MOT | SMD | The demonstration board also supports direct interfacing to audio decode | |
| WHC | (4) | TI | 07+ | Note 5: In applications where high power dissipation and/or poor package | |
| WHE | (1) | TI | SOP48W | 06+ | † TPS3106E09 and TPS3110K33 will be available in August 2001; all o |
| WHI | (9) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage ➃ Gate | |||
| WHK | (1) | Software selectable I O options (TRI-STATE output push-pull output weak | |||
| WHM | (4) | WANLON | 07+ | 70 | VBIAS (VCC, VBS1,2,3) = 15V, VS0,1,2,3 = VSS and TA = 25C unless otherwis |
| WHP | (16) | NAIS | 04 | All voltages are referenced to VSS = 0 V (ground). All characteristics | |
| WHR | (1) | debugging cycles. The logic, circuitry, and interconnects in the MAX II | |||
| WHS | (1) | Selects Burst Order. When tied to GND selects linear burst sequence. When | |||
| WHT | (10) | PhaseLink Corporation, reserves the right to make changes in its products | |||
| WI- | (31) | N/A | The AT88RF256 is an RFID (radio frequency identification) chip designed t | ||
| WI2 | (1) | N/A | The Code Warrior Integrated Development Environment is a sophisticated to | ||
| WI3 | (10) | Notes: 1. Contact a Cypress representative for industrial temperat | |||
| WI4 | (8) | N/A | 45321812 | The wide operating supply range and high accuracy make the LTC6101 ideal | |
| WI5 | (1) | TI | SSOP-56 | 01+ | Guaranteed by design. Not production tested. Sample tested du |
| WIA | (1) | The XC5200 CLB consists of four LCs, as shown in Figure 4. Each CLB has | |||
| WIB | (7) | NS | SMD | 2001 | Up to 9 channels Simultaneous two-channel sampling Sequential sampling |
| WIC | (13) | - | - | The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to i | |
| WID | (3) | N/A | The data inputs (SDIP/SDIN) and clock inputs (SCIP/SCIN)are internally te | ||
| WIE | (1) | • Double data rate architecture: two data transfers per cloc | |||
| WIF | (1) | N/A | 4532 | TTL Ground 1 TTL I/O Bit 0 TTL Direction Control ECL Direction Cont | |
| WIG | (1) | SIEMENS | SOP20 | 03+ | The time-domain maximum slope argument can be appropriate for non-sinusoi |
| WIJ | (4) | The VP-1000A is an advanced CMOS LSI chip for general purpose voice/soun | |||
| WIL | (2) | DIP | 97+ | Transmit Error Active high. When an error happened in the transmit data | |
| WIM | (5) | CHT | 3225-1R0M | 05+ | • Timer0: 8-bit timer/counter with 8-bit prescaler • Timer1: |
| WIN | (40) | WINBAN | 2002 | High performance 90 ns access time 25 ns page read times | |
| WIP | (3) | SD is a serial bi-directional data bus which is used to transfer address | |||
| WIR | (6) | 95+ | Input or Output Voltage (DC or Transient) (Referenced to VSS Vin, | ||
| WIS | (5) | AMIS | 07+ | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |
| WIT | (8) | The ADS-119 is a high-performance, 12-bit, 10MHz sampling A/D converter. | |||
| WIW | (1) | SHARMA | 07+ | Package drawings, standard packing quantities, thermal data, symbolizatio | |
| WJ3 | (5) | WJ | TO-4P | Reduced Threshold Voltages for LVTTL on Control Pine ♦ Eliminates | |
| WJ4 | (1) | PS-2 | Module | N/A | The 4 Mbit Flash memory array is organized into eleven blocks called se |
| WJ7 | (2) | N/A | DIP | 94 | VBIAS (VCC, VBS) = 12V, CL = 1000 pF, and TA = 25C unless otherwise specif |
| WJ9 | (1) | High-frequency EMI is best filtered at DXP and DXN with an external 2200p | |||
| WJA | (6) | SOP-8 | 00+ | Hynix HYMD116645B(L)8J-J series is unbuffered 184-pin double data rate Syn | |
| WJC | (7) | The IC requires only a common inexpensive capacitor in order to function. | |||
| WJD | (1) | Technology: high performance SiGe Bandwidth: 9 GHz Input noise current | |||
| WJE | (1) | LSI | 02+ | PLCC28 | A common ground is required between the input and the output voltages. Th |
| WJH | (1) | EAST LIGHT | DIP18 | OSC1, OSC2 are connected to an RC network or Crystal (determined b | |
| WJL | (45) | Cortina | 07+ | The AD1833A is fully compatible with all known DVD formats, accommodatin | |
| WJM | (1) | ||||
| WJR | (1) | Since front polarizer is easily damaged, pay attention not to scratch it. | |||
| WJS | (2) | 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ | |||
| WJW | (1) | SMD | 91+ | Hynix HYMD132G725A(L)8M-K/H/L series is Low Profile registered 184-pin dou | |
| WJZ | (2) | 3.3-V power. I/O 3.3-V circuit power terminals. A combination of high-fre | |||
| WK- | (2) | The three transmitter operating modes C transmit ASK, transmit OOK, and p | |||
| WK0 | (3) | The SOA curves combine the effect of all limits for this Power Op | |||
| WK1 | (1) | HEADIANEL | PLCC | 90+ | System and Device Block Diagrams Recommended Companion Components Device |
| WK2 | (13) | A4451 | The following is a list of advisories on modules in this version of silic | ||
| WK4 | (1) | *Absolute maximum ratings apply at 25C, unless otherwise noted. Stresses | |||
| WK5 | (4) | ||||
| WK8 | (2) | NEC | QFP | Each Peppermint board features a preprogrammed CY22393 embedded onto th | |
| WKA | (1) | Other | 07+ | To achieve proper device operation, an initial pause of 200 µs foll | |
| WKB | (1) | Notes: 5. AC characteristics (except High-Z) for all 8-ns and 10-n | |||
| WKC | (5) | MOT | 07+ | The WKC38XOV2.2 is a high precision, high throughput analog front end. T | |
| WKD | (1) | In-band Interference Rejection 20dB max. 2103dBm Sensitivit | |||
| WKK | (2) | 92 | The bq2060 uses a fully differential, dynamically bal- anced voltage-to-f | ||
| WKN | (1) | QFP240 | 0307+ | The Image Manipulation Sequencer can support any nearest- neighbor, bili | |
| WKO | (14) | temperature. System power may be further reduced using the optional disa | |||
| WKP | (14) | 0807+ | n Sector Protection C Any combination of sectors may be locked & | ||
| WKS | (3) | MICROCHIP | SMD18 | 07+ | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t |
| WKV | (1) | For BCP converters configured with the negative-polarity option on t | |||
| WL- | (6) | DIP16 | DIP16 | 02+ | The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR |
| WL0 | (6) | fagor | fagor | dc02 | These N-Channel enhancement mode power field effect transistors are produ |
| WL1 | (59) | N/A | 0402L | Areas where care in design must be observed are thermal ground, RF groun | |
| WL2 | (11) | MOT | 94 | Unlike other truly nonvolatile memory technologies, there is no write d | |
| WL3 | (12) | N/A | 1206L | † Package drawings, standard packing quantities, thermal data | |
| WL4 | (4) | SUM | TO-92 | 05+ | • High speed: propagation delay < 3.5 ns (max) • Very low C |
| WL5 | (5) | JDS | 光纤/金 | 07+/08+ | Gain Bandwidth Product: 10 MHz (typ.) Supply Current: IQ = 1.0 mA Supp |
| WL6 | (14) | AGERE | BGA196 | 05+ | Note: Some revisions of this device may incorporate deviations from publi |
| WL7 | (6) | JAT | SOT-89 | 04+ | Internal sample-and-hold Internal Reference Capability Dual gain sett |
| WL8 | (4) | MITEL | N/A | † Stresses beyond those listed under absolute maximum ratings may c | |
| WLA | (3) | WLA | BGA | N/A | FEATURES 1 A Output Current at 2.5 V 0.6 V Maximum Dropout Voltage at |
| WLB | (10) | LSI | TQFP-144 | 99 | A variety of frequency ranges and packaging options are available. The |
| WLC | (35) | 93 | FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN | ||
| WLD | (4) | WDC | 814 | The manufacturer and device codes can be accessed by software or hardware | |
| WLF | (1) | 05+ | 96 | QFN | 3. This input current only exists when the voltage at any of the input le |
| WLG | (1) | Thus when the voltage across the inductor is positive (State 1), the ind | |||
| WLI | (1) | 01 | CUSTOMER SERVICE CENTRES F FRANCE & BENELUX Les Ulis Cedex Tel: (1) | ||
| WLL | (2) | • Low-power, high-speed CMOS EPROM/ EEPROM technology R | |||
| WLM | (1) | LUCIDITY | SOP-24 | 800 mA Continuous Output Current Rating 30 V Output Voltage Rating Int | |
| WLN | (10) | If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 | |||
| WLO | (3) | • External components • External host for initialization | |||
| WLP | (4) | N/A | NEC | 04+ | DESCRIPTION These diode-transistor optocouplers use a ligh |
| WLR | (4) | The information provided herein is believed to be reliable at press time. | |||
| WLS | (4) | • Wide supply voltage range of 1.2 to 3.6 V • In accordance wi | |||
| WLT | (2) | Simplifies Circuit Design Reduces Board Space Reduc | |||
| WM- | (16) | PANASONIC | 袋装 | International Rectifiers R5 technology provides high performance power | |
| WM0 | (4) | The information contained herein is subject to change without notice. -Th | |||
| WM1 | (35) | WM | SOP | 07+ | When used as a decimating post-filter with a double speed oversampling an |
| WM2 | (12) | SILI | 08+ | Hynix HYMD512G726(L)4M-K/H/L series incorporates SPD(serial presence detec | |
| WM3 | (9) | N/A | N/A | N/A | When the device is configured for programmable flags and both WEN2/LD a |
| WM5 | (5) | VISHAY | CAN3 | The configurable non-multiplexed microprocessor port allows users to progr | |
| WM6 | (10) | GLENSAYRE | 2000 | 400 MSPS Internal Clock Speed Integrated 14-bit D/A Converter Programmab | |
| WM7 | (2) | 912 | WOLFSON | 9800 | By using the control signal CS, SK and data input signal DI, these instru |
| WM8 | (351) | WOLFSON | SSOP 28P | 03+ | When the CAT34AC02 begins a READ mode, it transmits 8 bits of data, rel |
| WM9 | (105) | WM | QFP | 05+ | Fifth Generation HEXFETs from International Rectifier utilize advanced p |
| WMB | (2) | 97 | Stresses beyond those listed under "absolute maximum ratings" m | ||
| WMC | (9) | Highest sustained bandwidth per DRAM device • 8000/6400/4800 MB/s | |||
| WMF | (7) | Beneficial comments (recommendations, additions, deletions) and any perti | |||
| WMG | (2) | To achieve the ever-present need for smaller, faster, lighter devices tha | |||
| WMI | (10) | HDRIVE, LDRIVE: The outputs of the PWM are totem pole MOSFET gate driver | |||
| WML | (3) | MITSUMI Y | 03+ | The insertion loss measurement was taken by connecting two baluns back to | |
| WMM | (5) | 27 | WM | 0026+ | The ISL6433 monitors all the output voltages. A single Power Good signa |
| WMO | (1) | Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, | |||
| WMP | (1) | N/A | SMD | 03+ | Address Strobe from Processor, sampled on the rising edge of CLK. When a |
| WMQ | (1) | NS | SOP | 1992 | PWM signal can be reflected in turn-on signal by supplying PWM sig |
| WMR | (1) | (LX)high-frequency | Up to 18 A Output Current 12-V Input Voltage Wide-Output Voltage Adjust | ||
| WMS | (35) | WINBOND | 0318+ | SSOP | Make sure the decoder MFBAH/L0 and MFBAH/L1 registers are set so that an |
| WMV | (1) | Acknowledge Acknowledge is a software convention used to provide a posi | |||
| WMY | (3) | ADCAOFR | |||
| WN- | (2) | 2008 | − 15-kV − Human-Body Model Meets or Exceeds the Requirements | ||
| WN0 | (1) | 07+ | 3. Measured by the voltage drop between A and B pins at the indicated cur | ||
| WN1 | (11) | TO-92 | NOTES: 1. W is high for read cycle. 2. All timings are refer | ||
| WN3 | (1) | SOP | 04+ | JLC1563 is an I2CCbus signal transceiver and conditioner. Current | |
| WN4 | (1) | PHILIPS | 01+ | 3. "Maximum allowable voltage" is that value at maximum contact | |
| WN5 | (1) | SILICONI | CAN3 | An access time of 90, 100, 110, or 120 ns is available. Note that each | |
| WN6 | (1) | HARRIS | 2008 | The adjustable output device has an output voltage range of 1.25 | |
| WN7 | (1) | SMD | 03/+04+ | The ZL30414 is an analog phased-locked loop which provides rate conversion | |
| WN8 | (2) | WN | QFN-32 | N/A | • The TOSHIBA products listed in this document are intended for usag |
| WN9 | (1) | SEIKO | 08+ | ||
| WND | (2) | ST | SMD-16 | 02+ | Tiny SOT−353 and SOT−553 Packages 2.7 ns TPD at 5 V (typ) So |
| WNG | (2) | • Voltage Supply -2.7 ~ 3.6 V • Organization | |||
| WNI | (1) | T | PLCC | 00/01 | The I2C bus is a simple two-wire bidirectional serial interface. It contr |
| WNP | (1) | clock cycle Interleaved auto refresh mode Programmable burst lengths and | |||
| WNQ | (1) | Stresses above these ratings may cause permanent damage. Exposure to abso | |||
| WNS | (1) | N/A | DIP40 | 06+ | The MT90826 Quad Digital Switch has a non-blocking switch capacity of 4,09 |
| WO- | (1) | 2.1.1 Specifications, standards and handbooks. The following speci | |||
| WO0 | (1) | me | me | dc95 | The WO08 is a low skew 1CtoC10 differential driver, designed with |
| WO1 | (1) | TOS | The TPS793xx family of low-dropout (LDO) low-power linear voltage regul | ||
| WO2 | (2) | Speed grade update to preliminary status, Power-on specification and Cloc | |||
| WO3 | (2) | Stresses beyond those listed under absolute maximum ratings may cause pe | |||
| WOD | (1) | stock | This is a bidirectional pin used to transfer addresses and data into an | ||
| WOG | (1) | DESCRIPTION The 74AC573 is an advanced high-speed CMOS OCTAL D-TYPE LA | |||
| WON | (1) | The LM2696 is a pulse width modulation (PWM) buck regu- lator capable o | |||
| WOO | (1) | SMD28 | Decrementer, time base, and real-time clock (RTC) from the PowerPC | ||
| WOR | (6) | SAM | SOP44W | 2007+ | Frequency select latch input pin / 14.318 MHz reference clock. Supply fo |
| W-P | (1) | The integrated circuit U6803B requires a stabilized supply voltage (VS = | |||
| WP- | (138) | SC LK A | 94 | • High Efficiency Linear Regulators • Post Regulators for Swit | |
| WP0 | (18) | The LTC®1628-SYNC is a high performance dual step- down switching reg | |||
| WP1 | (40) | 03+ | BGA/9*9 | The UC382 is easy to use. The adjustable version requires two 0.1% resist | |
| WP2 | (23) | N/A | CYPRESS | 04+ | This document contains information on a product under development at Adva |
| WP3 | (15) | ANSTEK | 05+ | QFP | A 400 Ω resistor in series with the input provides some phase advan |
| WP4 | (3) | These voltage regulators are monolithic integrated circuits designed as fi | |||
| WP5 | (28) | IOR | SMD | 97+ | The WP50012L46E family of FPGAs offers four devices at the low end of th |
| WP6 | (2) | NSC | DIP-8 | Advanced Process Technology Ultra low On-Resistance Provides Higher Effic | |
| WP7 | (21) | WP | Features include soft-start, input undervoltage lockout (UVLO) and Powe | ||
| WP8 | (1) | INTEL | BGA | 05+ | Loudspeaker amplifier power supply input An external power supply connec |
| WP9 | (914) | N/A | TI | 04+ | The AD8021 is not only technically superior, but also priced considerabl |
| WPA | (5) | shinway | shinway | dc02 | The device is accessed by a simple serial interface that is SPI-compatib |
| WPC | (24) | powercon | powercon | dc01 | ADDRESS STROBE: This is an active high signal used to control latching of |
| WPD | (5) | iomega | 01+ | The output drivers in the HIP6601B, HIP6603B and HIP6604B have the capa | |
| WPE | (2) | The TLC3541 and TLC3545 are a family of high performance, 14-bit, low p | |||
| WPG | (1) | WORLD | N/A | 2007 | In Discontinuous mode, when the inductor current drops to zero, the vol |
| WPI | (8) | Directly placing semiconductor transient protection devices or MOV's on | |||
| WPJ | (1) | 98+ | PLCC | DESCRIPTION This Power Mosfet is the latest development of STMicroelect | |
| WPL | (1) | . | . | 30 | The DDX-2000 converts serial I2S digital audio signals into pulse-width-m |
| WPN | (18) | NULL | N/A | H2 The second harmonic arises from the input stage, and the lower the ap | |
| WPO | (2) | IR | TO-247 | 05+ | The steady state life test of step 1 shall be extended to 1,000 hours for |
| WPP | (2) | 94 | Six High-Side and six Low-Side-Drivers Free configurable as switch, halfb | ||
| WPQ | (4) | NS | 98 | You can, however, measure the V-I demand of a motor (or any other load) | |
| WPS | (3) | TEXAS | SOP14 | 07+ | When starting up the circuit utilizing the MSK 4301 for the first time, |
| WPT | (2) | IXYS | 04+ | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |
| WPU | (2) | The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced | |||
| WQ0 | (1) | This voltage is made in an external loop filter and sent to VCO's input b | |||
| WQ1 | (1) | WINBOW | DIP | TMIN = −40C, TMAX = +85C. Typical values are at TA = 25C, clock fre | |
| WQP | (1) | Zilog | 00+ | DIP-28 | The SDRAM employs state-of-the-art technology for high performance, relia |
| WR- | (53) | JAE | 07+ | *3 Transient peak current (Itm) The peak current rating, Itm, is | |
| WR0 | (229) | PILKOR | 05+ | All devices are 100% production tested at +25C and are guaranteed by desig | |
| WR1 | (57) | Module | 94 | TstgStorage temperature range2C65+150C NOTES: 1. Stresses beyon | |
| WR2 | (50) | NA | 06+ | 66/133-MHz, 64-bit, true multifunction PCI-X host bus interface Backwar | |
| WR3 | (13) | N/A | IGBT | 2005+ | Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Du |
| WR4 | (54) | vishay-gro | n/a | Samsung products are not designed, intended, or authorized for use as com | |
| WR5 | (8) | vishay-gro | n/a | per Figure 5 Waveform Peak Power − Min. 150 W @ 20 ms (Unidirection | |
| WR6 | (24) | RET | DIP16 | An output capacitor of at least 10uF must be used to insure stability o | |
| WR7 | (10) | . | . | 3 | The CD4001B, CD4002B, and CD4025B types are supplied in 14-lead hermetic |
| WR8 | (1) | The ADCMP565 is an ultrafast voltage comparator fabricated on Analog Dev | |||
| WR9 | (12) | Winbond | Converts Y, Cr, Cb data to analog RGB and composite or S-video and comp | ||
| WRA | (5) | MORNSUN | 08+ | RIN=30Ω, CIN=10µF, RL=499Ω, unless otherwise specified. | |
| WRB | (21) | MORNSUN | 08+ | The system clock for the microcontroller is derived from either 6MHz or 1 | |
| WRC | (11) | western | western | dc02 | The high efficiency of the HPR2XX Series means less internal power dissi |
| WRD | (17) | MORNSUN | ORG PACKING | 08+ | |
| WRF | (1) | The small size and battery-powered operation associated with LCD-equipped | |||
| WRG | (1) | The AGB3302 is one of a series of high performance InGaP HBT amplifiers | |||
| WRI | (34) | Extended Data Out (EDO) Operation CAS-Before-RAS ( CBR) Refresh High-Imp | |||
| WRM | (14) | This pin has an on-chip 1.0MΩ pullup resistor. An a.c. coupled si | |||
| WRN | (1) | The RESET output is guaranteed to be in the correct state with V CC down | |||
| WRO | (1) | N/A | N/A | N/A | Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data r |
| WRS | (1) | The AVR uses a Harvard architecture concept C with separate memories and | |||
| WRU | (1) | N/A | Connect this pin to the upper MOSFETs gate. This pin provides the PWM-con | ||
| WS- | (14) | SHARP | QFP | A 5% resistor value is recommended. In the OOK mode, this pin is usually | |
| WS/ | (1) | The 64-bit wide memory array provides the system with an 800MB/s peak b | |||
| WS0 | (1) | NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung | |||
| WS1 | (27) | 铁帽 | 08+ | Frame rate: 30/15/10/5/4/3/2/1 fps Sub-sampling quarter mega pixel for | |
| WS2 | (103) | WSI | 00+ | The AT17F Series of In-System Programmable Configuration PROMs (Configura | |
| WS3 | (8) | WS | TO-92 | 07+ | A/D Mute Toggles mute status at the rising edge. If this pin is not used |
| WS4 | (7) | N/A | 2450 | LINEARITY ERROR (also called INTEGRAL NONLINEAR- ITY OR INL): Analog Dev | |
| WS5 | (294) | WSI | 99+00+ | 4503 | The MHF converters are switching regulators which use a quasi- square wa |
| WS6 | (26) | WSI | 07+ | rejection, when an erroneous result occurs, the software routine should in | |
| WS7 | (23) | WIN | 91+ | QFP/160 | † Stresses beyond those listed under absolute maximum ratings may c |
| WS8 | (4) | WS | SOP | 212 | PAGE READ: The page read operation of the device is controlled by CE, OE, |
| WS9 | (6) | 91 | |||
| WSA | (7) | WSA | SOP28 | 0611+ | |
| WSB | (5) | N/A | NOTE: Device will meet the specifications after thermal equilibrium has b | ||
| WSC | (92) | N/A | CLOCK SYNC- is an input for synchronizing to an external clock. The sync | ||
| WSD | (23) | WS | DIP | Notes: 6. Test conditions assume signal transition time of 3 ns or | |
| WSF | (5) | Input bus select / I2C clock input. The operation of this pin depends on | |||
| WSH | (1) | N/A | N/A | • Automatic power-down • Expandable data bus to 32/36 bits or | |
| WSI | (365) | WSI | DIP | Each XC5200 CLB contains four independent 4-input func- tion generators | |
| WSK | (8) | WST | 263 | 07+ | Leads are Readily Solderable • Lead and Mounting Surface Temp |
| WSL | (455) | N/A | Stereo Codec: DAC SNR 98dB, THD -84dB (A weighted @ 48kHz) ADC SNR 90dB, | ||
| WSM | (6) | This IC was developed as an interface IC for video equipment having a smal | |||
| WSN | (9) | (1) Stresses beyond those listed under absolute maximum ratings may cause | |||
| WSP | (3) | Notes: 1. Absolute maximum I/O pins is maximum pin count minus 8. Additio | |||
| WSQ | (1) | TOTO-KOTTO | QFP | 04+ | Data is shifted out of the FIFO on the falling edge of the SO signal. Th |
| WSR | (88) | N/A | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN | ||
| WSS | (4) | W.S.S | QFP100 | 00+ | C175CmAIndustrialfCLOCK = 1 MHz One output at a time for a maxim |
| WST | (5) | WST | 2007 | Laser mode hopping noise during read mode can be reduced by the use of an | |
| WSW | (23) | hughes | hughes | dc72+ | Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the a |
| WSZ | (1) | SIEMENS | DIP-22 | NOTES: 1. Dimensions are in inches. Metric equivalents are given f | |
| WT- | (6) | N/A | DIP | N/A | The device integrates complete interfaces to stereo or mono microphones a |
| WT0 | (11) | Panasonic | ZIP-6 | 07+/08+ | The HC4066 and CD74HCT4066 contain four independent digitally controlle |
| WT1 | (9) | WINCAN | LQFP-128 | 2004 | The information contained herein is presented only as a guide for t |
| WT2 | (33) | 2008 | • 2GHz gain-bandwidth product • Gain-of-10 stable • | ||
| WT3 | (6) | VHTCCH | DIP | 4 | Operation is synchronous and the device is edge-triggered on the LOW to |
| WT4 | (4) | 01+ | |||
| WT5 | (6) | WELTHEND | QFP | 2002 | When the CH7009 is operating as a VGA to TV encoder in master clock mod |
| WT6 | (79) | Weitfend | 2 | NOTES: 1. For conditions shown as Min. or Max., use the appropriate valu | |
| WT7 | (35) | N/A | OKI | 04+ | The LM1881 Video sync separator extracts timing informa- tion including |
| WT8 | (109) | 95/96 | The CPU controls the PWM output by setting the TPU parameters. The Stator | ||
| WT9 | (2) | Weltrend | DIP | 04+ | A refresh operation must be performed at least once every 16 ms (128 ms f |
| WTA | (14) | QFP | 1997 | Notes: Stresses greater than those listed under MAXIMUM RATINGS may cau | |
| WTB | (7) | Airborn | 06+ | Function Standby Read Write: Word (Early Write) Read-Write EDO Page-M | |
| WTC | (8) | SOP | The pre-bias current is controlled by the pin VPRE and can be controlled | ||
| WTD | (3) | 00 | 2. Indirect addressing resources (registers and initial load memory) &nb | ||
| WTI | (1) | system clocks (At a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TC | |||
| WTK | (4) | KB | 裸片 | 04+ | Ÿ Miniature, cost-effective switching solution. Ÿ State of the |
| WTL | (5) | 973 | Hynix HYMD232726(L)8-K/H/L series incorporates SPD(serial presence detect) | ||
| WTO | (1) | JKC | The LVDS388 and LVDT388 (T designates integrated termination) are eight | ||
| WTP | (1) | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |||
| WTS | (1) | WINBOND | 07+ | This document is a general product description and is subject to change wi | |
| WTT | (4) | Maximum Output Current: 250 mA. Highly Accurate Output Voltage +/- 1.4% | |||
| WTU | (2) | SOP34 | 01+ | Memories C 1K or 2K bytes Program memory (OTP, EPROM, FASTROM or | |
| WTV | (2) | ADC data outputs are internally connected directly to the receivers digi | |||
| WU- | (3) | The Customer Demonstration Board provides the ROC093XC radio with a PIC mi | |||
| WU1 | (2) | wustlich | wustlich | dc01 | EBEN selects the functionality of Port 5 and Port 6 When EBEN is low the |
| WU2 | (2) | wustlich | wustlich | dc02 | The blanking control input on the hexadecimal displays blanks (turns o |
| WU4 | (2) | The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM i | |||
| WU7 | (1) | wustlich | wustlich | dc94 | Current Word Register Each channel has a 16-bit Current Word Count regist |
| WUA | (1) | The digital controlled potentiometer is implemented using 1023 resistiv | |||
| WUB | (6) | vossloh | vossloh | dc05 | The CS4344 family is based on a fourth order multi-bit delta-sigma modula |
| WUH | (1) | vs | vs | dc0442 | The IP4001S has a thermal protection against the abnormal operation. When |
| WUJ | (12) | The SN74CBT16210C is a high-speed TTL-compatible FET bus switch with low | |||
| WUT | (1) | 2.88MB Super I/O Floppy Disk Controller − Relocatable to 480 Diffe | |||
| WUW | (3) | NTT DaTa | 98 | The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8- | |
| WUX | (1) | NS | SOP-20 | 00-01+/SX | Notes: 1. The luminous intensity is measured on the mechanical axis of t |
| WUY | (1) | wustlich | wustlich | dc03 | DYNAMIC PERFORMANCE Maximum Output Update Rate (fDAC) Output |
| WV0 | (2) | Notes: (1) The ISR will operate at no load with reduced specifications. | |||
| WV3 | (4) | Motorola reserves the right to make changes without further notice to any | |||
| WV5 | (1) | NA | DIP | 98 | The attached spice model describes the typical electrical characteristics |
| WV8 | (1) | .. | SOP | 00+ | The OPA341 series rail-to-rail CMOS operational amplifiers are designed |
| WVA | (1) | PLESSEY | DIP | n/a | 5-mm-LED-Gehäuse (T 13/4), schwarz eingefärbt, Anschluß i |
| WVJ | (1) | Resolution: Accelerometers can be used in a wide variety of low g applica | |||
| WVM | (1) | ||||
| WVT | (2) | MITEL | QFP | 04+ | There are five selectable modulation schemes: binary frequency shift key |
| WW- | (3) | NSC | 2008 | guarantees lower guaranteed maximum supply current than competing produc | |
| WW0 | (1) | NSC | 2008 | Design and specifications are subject to change without notice. Ask | |
| WW1 | (5) | NSC | 2008 | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | |
| WW2 | (4) | N/A | The PLL post-divider N is configured through either the serial or | ||
| WW4 | (1) | • Gain calibration, to compensate for gain errors (in Kv and | |||
| WW9 | (2) | NSC | PLCC-44P | 00+ | Current Limit Protection Isolation Test Voltage 5300 VRMS Typical RON |
| WWI | (2) | The three package styles available provide a magnetically optimize | |||
| WWM | (1) | LINEAR | SOT23-5 | 05+ | The intended application of these devices and signaling technique is bo |
| WWN | (2) | ||||
| WWP | (3) | SONY | The EBD10RD4ADFA is 128M words 72 bits, 1 rank Double Data Rate (DDR) SD | ||
| WWR | (1) | The CXD2931R is capable of receiv- ing signals from 16 satellites at the | |||
| WWT | (1) | The HT24LC16 has a write protect pin that provides hardware data protecti | |||
| WWW | (5) | TECH | DIP | 2000 | Output current pulses are enabled when an L signal is applied to the WE |
| WX- | (1) | TWATSU | 16-bit programmable input frequency divider (including a 32/33 prescaler) | ||
| WX1 | (2) | DIP | 98 | Keep safety first in your circuit designs! 1. Renesas Technology Corpor | |
| WX2 | (3) | N/A | VIN and VOUT Limited Only by External Components Adjustable Slope Compens | ||
| WX5 | (1) | 99 | Analog signals should be inputted through AIL and AIR pins. The signals t | ||
| WX7 | (1) | NRS | SMD | 04+ | For enhanced performance, the VRE304 has an external trim option for user |
| WX8 | (1) | NRS | 03+ | • 4000 Watts for One Microsecond Square Wave or 14,000 watt | |
| WXE | (4) | Maximum ratings are those values beyond which device damage can occur. Ma | |||
| WXT | (1) | The LTC®3717 is a synchronous step-down switching regulator controlle | |||
| WY0 | (9) | vishay | vishay | dc99 | Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Addr |
| WY2 | (1) | The M36L0R7050T0 and M36L0R7050B0 com- bine two memory devices in a Mul | |||
| WY4 | (2) | SOP 2.5.9Process critical and key parameters 0076604 Process Qualificatio | |||
| WY9 | (1) | WINBOW | DIP | HARDWARE FEATURES Any combination of sectors can be erased | |
| WYA | (1) | Double metal process for low gate resistance International standard pa | |||
| WYE | (11) | ZIVA | 02+ | Small Compact Surface Mountable Package with JCBend Leads Rectangular P | |
| WYF | (5) | 07+ | Floppy Disk Controller (FDC) Software compatible with the PC8477 (the P | ||
| WYO | (16) | VISHAY | O7+ | The LVTH241 devices are organized as two 4-bit line drivers with separa | |
| WYW | (1) | CYPRESS | 06+ | 500 | When a valid DTMF signal burst is present, ESt or DStD will go high. The |
| WZ- | (1) | AH174 is a single-digital-output Hall-effect sensor for high temperature | |||
| WZ0 | (4) | Differential clock input. The TFP513 supports both single-ended and fully | |||
| WZ1 | (73) | at 9-A Continuous Output Source or Sink Current Disabled Current Sinking | |||
| WZX | (2) | The attached datasheets are provided by SAMSUNG Electronics. SAMSU |
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