| Mfg | pack | D/C | Descrpion | ||
| X.D | (1) | Supports Direct Memory Access (DMA) Bursts With 64-Byte FIFO Supports EP | |||
| X.J | (1) | These circuits perform a single function: they assert a reset signal when | |||
| X0- | (12) | Positive digital supply pin for the X0-055BHT-20.48000s output drivers. | |||
| X00 | (67) | N/A | 06+ | 500 | A: The value of R JA is measured with the device mounted on 1in2 FR-4 boar |
| X01 | (60) | MICROSOFT | 1. Units in the JPP-21S series of Quadraphase Modulators are composed of | ||
| X02 | (118) | AT&T | QFP64 | Beneficial comments (recommendations, additions, deletions) and any perti | |
| X03 | (45) | N | CapabilitiesLogic Analyzer State per clock modeprovides a Configurations | ||
| X04 | (74) | ST | TO-202 | 06+ | When the device is configured for programmable flags and both WEN2/LD a |
| X05 | (51) | SHARP | . | 6 | ➀ Models are specified at "full load" (5V & 3. |
| X06 | (48) | SHARP | Each red, green and blue current output should have a load resistor conn | ||
| X07 | (42) | NEC | 2003 | I2C is a trademark of Philips Corp. Purchase of I2C components from Maxim | |
| X08 | (35) | SHARP | DIP64 | 92+ | The ISL6440 provides the power control and protection for four output v |
| X09 | (47) | SHARP | Input serial data at rising edge of shift clock, starting from the low or | ||
| X0D | (1) | The TL7702B, TL7705B, and TL7733B are integrated-circuit supply-voltage | |||
| X0M | (1) | TI | 04+ | The µPA1853 is a switching device which can be driven direct | |
| X0S | (1) | Hynix HYMD216M646(L)6-K/H/L series is unbuffered 200-pin double data rate | |||
| X0T | (1) | The module should be placed as close as possible to the transmitter or re | |||
| X-1 | (4) | additional logic Full synchronous operation on both ports C 4ns setup to | |||
| X10 | (26) | 仙童 | 袋装 | Picture Structure Improvement including Color Transition Improvement, L | |
| X11 | (23) | TEXAS | QFP | 98+ | The transition from VIH to VID must be slower than tPHPHH. Ready/Busy |
| X12 | (185) | INTERSIL | SMD-8 | 07+ | The bq2902 is a low-cost charger for rechargeable alkaline batteries such |
| X13 | (48) | HAR | TO92 | 2000 | The DS1554 is a full function, year 2000-compliant (Y2KC), real-time cloc |
| X14 | (11) | 08+ | 5V power supply 5V power supply 5V LNA power supply RF input LNA grou | ||
| X15 | (21) | INTERSIL | SOP-16 | 01+ | As with any RF circuit, the layout of the X153318C X153318 circuits affec |
| X16 | (27) | UART0 and UART1 can operate using an internal clock at 230 KBaud with n | |||
| X17 | (56) | PLCC | 04+ | Note: 1. Enhancement mode technology employs a single positive Vg | |
| X18 | (18) | IC | SOP | Though they're not complicated, schemes for debouncing a pushbutton switch | |
| X19 | (3) | SHARP | DIP | The standard PC chipset functions (DMA, interrupt controller, timers, p | |
| X1C | (7) | Sony Ericsson Mobile Communications AB offers mobile communications produc | |||
| X1D | (1) | The equalizer improves the cable-induced jitter; the data slicer restor | |||
| X1E | (3) | EPSON | 07+ | As seen in the block diagram, these encoders contain a single Light E | |
| X1G | (3) | EPSON | 4200 | The MAX1978 operates from a single supply and provides bipolar 3A output | |
| X1P | (1) | This specification contains ADVANCE INFORMATION data. ISSI reserves the r | |||
| X1T | (1) | The TMC249 is a dual full bridge driver IC for bipolar stepper motor con | |||
| X-2 | (1) | The FM811 has an active low RESET output, while the FM812 offers an acti | |||
| X2- | (40) | JS | 05+ | The X2-102K is a 16-bit, low-power, successive- approximation analog-to-d | |
| X2( | (1) | In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have | |||
| X20 | (126) | XICOR | PLCC | 00+ | 1.3.3 WATCHDOG Timer The X20C16JI-35SXL WATCHDOG timer, CH2, is a protec |
| X21 | (22) | XICOR | 1000 | 01+ | |
| X22 | (84) | XICOR | DIP | 06+ | Please be aware that an important notice concerning availability, |
| X23 | (14) | BGA | • Microcontroller support; only for control, no specific des | ||
| X24 | (632) | SHARP | 02+ | SOP | The HR700 converters are manufactured using techniques that provide very |
| X25 | (549) | 01 | Data is latched into input registers and remains loaded until next LOW | ||
| X26 | (5) | N/A | 03+ | MEMORY ARRAY ORGANIZATION The 1 MByte Flash memory array is organized in | |
| X27 | (10) | XICOR | 03+ | The coupler consists of a AlGaAs LED that is optically cou- pled to a die | |
| X28 | (865) | XICOR | DIP24 | 2007+ | Notes: 1. Only under quienscent conditionsno RF applied. 2. VDD = 7.0V, |
| X29 | (11) | MOTOROLA | 00+ | RST Reset input A high on this pin for two machine cycles while the oscil | |
| X2A | (3) | The ISL6118 has integrated current sensing on the power MOSFETs that allo | |||
| X2B | (2) | The LT ®1186F is a fixed frequency, current mode, switch- ing regula | |||
| X2C | (3) | NSC | 2001 | -Port 92 Support -Fast Gate A20 and KRESET Outputs Serial Ports -Two Fu | |
| X2D | (2) | XICOR | 1000 | use by multiple AHB Bus Masters 32-bit 66/33 MHz PCI Host and Satellite | |
| X2L | (2) | ST | SOP | The interface should be arranged to allow simple data transmission from t | |
| X2N | (207) | CAL | CAN | If the attached printer is powered off, both SELECT OUT and BUSY will b | |
| X2P | (1) | NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than | |||
| X2R | (4) | The phase detector and the M divider force the VCO output frequency to | |||
| X2S | (3) | MOTOROAL | SOT-423 | 05+ | 1. Can be used in VCR and TV channel selection systems, and also for blue- |
| X2T | (1) | TI | 07+ | Of our low-temperature polycrys- talline silicon LCD products, the X2TLK | |
| X2U | (2) | HIT | SOP | 2003 | During power-up, all programming modes of operation are inhibited until |
| X2W | (1) | N/A | DIP2 | 06+ | Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pin |
| X2X | (1) | ROHM | QFP | 02+ | Macrocell registers can be clocked from one of several global or produc |
| X-3 | (7) | MC | SOP20 | 02+ | The VP-1000A is an advanced CMOS LSI chip for general purpose voice/soun |
| X3- | (1) | N/A | This device is a 16-bit edge-triggered D-type flip-flop featu | ||
| X30 | (14) | Reduced harmonic content of input currents corresponding to standards | |||
| X31 | (15) | XICOR | TSSOP28 | Information furnished is believed to be accurate and reliable. However, S | |
| X32 | (20) | MOT | SOP8 | 04+ | The X3200Z is a miniature 1-Form A solid state relay in a 4 pin SOP packa |
| X33 | (10) | SAW | 98 | Note 2: Absolute maximum ratings are those values beyond which damage to | |
| X34 | (3) | ST | 07+ | Extended frequencies are only available via SMBUS interface. They are acc | |
| X35 | (3) | 10 | ST | 03+ | The X350C is a high-performance CMOS static RAM or- ganized as 65,536 w |
| X36 | (2) | ||||
| X37 | (32) | 98 | PLCC-44 | Stereo Codec: DAC SNR 98dB, THD -84dB (A weighted @ 48kHz) ADC SNR 90dB, | |
| X38 | (6) | ST | 07+ | 2.Controlling dimension : millimeters. 3.Maximum lead thickness includes | |
| X39 | (13) | MOT | QFP | 97+ | When presented with a composite video input signal, the GS4882 outputs co |
| X3C | (1) | The AHCT574 devices are octal edge-triggered D-type flip-flops that fea | |||
| X3D | (1) | XICOR | 1000 | 01+ | Loss of Signal The Loss Of Signal (LOS) output indicates an unusable o |
| X3M | (4) | Intel and Pentium are registered trademarks of Intel Corporation. Lexmark | |||
| X3N | (135) | CAL | CAN | Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS | |
| X3P | (5) | MOT | 95 | For both packages, the RÈJAvalues were computed using JEDEC high | |
| X3R | (2) | SSMD | 92 | The WRITE instruction includes 16 bits of data to be written into the s | |
| X3S | (1) | The big advantage of this approach compared to a single DAC running at ha | |||
| X-4 | (1) | If the underlying voltage noise mechanism of the sampling jitter has a wh | |||
| X40 | (311) | intersil | intersil | dc0438 | Programs compiled natively on the host can not run on the target Program |
| X41 | (42) | QFN | 0717+ | † Stresses beyond those listed under absolute maximum ratings may c | |
| X42 | (28) | XICOR | CHIP SELECT: A low on this pin during the falling edge of ALE allows a re | ||
| X43 | (35) | TI | QFP | 00+ | • Space Saving SIP Package • +5V input • 5-bit Program |
| X44 | (33) | ST | 00+ | Electrical Characteristics / Ta=25C Drain to Source Breakdown Vol | |
| X45 | (18) | SOIC/3.9mm | These power modules are a series of high performance, 8-A rated, | ||
| X46 | (24) | ST | 07+ | VERY LOW DROPOUT VOLTAGE (0.45V) VERY LOW QUIESCENT CURRENT (TYP. 50 | |
| X47 | (2) | 6 | MOTOROLA | 99+ | This new generation of TRENCH MOSFETs from Zetex utilizes a unique struct |
| X48 | (4) | ST | 2.5V to 20V Step Down Achieved Using Dual Input Output Voltage down to | ||
| X49 | (9) | MOT | SOP16S | 2007+ | 1. 10 X 1000 ms, non−repetitive 2. 1 square copper pad, FR− |
| X4C | (5) | XICOR | 7.4.4 NAT: RFC1631, 2663 The Network Address Translator (NAT) implements | ||
| X4D | (2) | SOP | 3-V Operation Two Differential Microphone Inputs, One Differential Earph | ||
| X4G | (1) | MURATA | 06+ | Memories C 1K, 2K or 4K bytes Program memory (OTP, EPROM, FASTRO | |
| X4M | (2) | 12 parallel channels, total 32.6 Gbps capacity Data rate up to 2.72 Gbps | |||
| X4N | (2) | FAICHILD | TO92 | Low-latency option Skew alignment support for multiple bytes of of | |
| X4R | (1) | SOP34W | 2007+ | coupling from the supply. Also, place the VCO as far away as possible fro | |
| X50 | (232) | INTERSIL | SOP8 | 0550+/0616+ | Parameter Supply Voltage VDD to Ground Data Input, Data Output, VB Colu |
| X51 | (204) | N/A | Intersil(Xicor) | 04+ | The information herein is given to describe certain components and shall |
| X52 | (8) | MOTOROLA | 99+ | assure the safety of the circuits in the reverse bat- tery condition a | |
| X53 | (167) | XICOR | 1000 | 01+ | BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 |
| X54 | (4) | LUCAS | 00+ | NOTE: Device will meet the specifications after thermal equilibrium has b | |
| X55 | (7) | XICOR | 0 | This device is an advanced direct conversion receiver for operati | |
| X56 | (77) | ST | SOP20 | when the CLOCK INHIBIT signal is high. A high RESET signal clears the c | |
| X57 | (8) | ST | 07+ | The P/R input is latched by the falling edge of the CE pin. A HIGH level | |
| X58 | (7) | QFP32 | In conjunction with the V103 transmitter, the V104 can transmit 10 bits p | ||
| X59 | (1) | The FPD-Link receiver supports graphics controllers with Spread Spectrum | |||
| X5B | (3) | MOT | PLCC | 04+ | NOTES: 1. When dc coupling to the OSCin pin is used, the pin must be driv |
| X5D | (2) | TDK | PLCC28 | 03/+04+ | UV/OV PINCCUNDERVOLTAGE AND OVERVOLTAGE DETECTION Undervoltage Fal |
| X5F | (2) | XICOR | 97+ | 100 | The PowerInfo 2 board is a simple, easy to use hard- ware interface tha |
| X5M | (2) | G.703 2048kHz Synchronization Interface Compliant G.703 64kHz Centralize | |||
| X5O | (1) | XICOR | DIP | 06+ | This datasheet contains new product information. Myson Technology reserves |
| X5P | (1) | VTECH | PLCC44 | 07+ | AMD MirrorBit flash technology combines years of Flash memory manufactu |
| X5R | (1) | SOP36W | 2007+ | BB Filter BW Control Dynamic Range Adjust Dynamic Range Adjust Posit | |
| X5T | (2) | ST | 07+ | Teccor manufactures 15 A rms to 25 A rms rectifiers with volt- ages rated | |
| X60 | (69) | XICOR | The ISL6118 has two shutdown modes. When disabled with a load current les | ||
| X61 | (4) | 3 | 06+ | Figure 12 shows a dual-trace photograph of a triangular signal being sa | |
| X62 | (2) | MOTOROLA | 00+ | POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Thr | |
| X63 | (6) | XICOR | QFP | 02+ | |
| X64 | (9) | ST | 00+ | 22 | Note 2: Electrical Table values apply only for factory testing conditions |
| X65 | (9) | TI | QFN-48 | 05+ | The HS-0546RH and HS-0547RH are radiation hardened analog multiplexers |
| X66 | (2) | ||||
| X67 | (9) | STR | 00+ | TO3P-7P | (Before using this chip, take a look at the following description note, it |
| X68 | (45) | XICOR | 08+ | The X68C64PIA is a three-stage UHF amplifier module in a SOT482C leadles | |
| X69 | (26) | EPCOS | 9520 | Notes: 1. For Max. or Min. conditions, use appropriate value specified un | |
| X6D | (2) | Parameter POWER REQUIREMENTS VCC VDD VSS | |||
| X6S | (2) | The Hynix X6SD1960-X20-3CC Series are Dual In-line Memory Modules s | |||
| X7- | (1) | 4. DC/DC, PECL for Signal Detect PECL compatible. Load is 50 ͐ | |||
| X70 | (14) | ATI | BGA | 04+ | |
| X71 | (5) | N/A | N/A | N/A | The MC68HC000 is an implementation of the M68000 16/-32 bit microprocesso |
| X72 | (6) | TI | SOP | 06+ | An open drain FAULT pin will indicate that a fault has occurred. The fa |
| X73 | (9) | EPCOS | SMD | 2005PB | VREFL Lch Voltage Reference Input Pin, AVDD Normally, connected t |
| X74 | (3) | MOTOROLA | O7+ | Signal Processor (DSP) TMS320C6701 C 8.3-, 6.7-, 6-ns Instruction Cycle T | |
| X75 | (6) | TI | 2005 | 2. Timer Data Reading When the I/O termianl is "L" and | |
| X76 | (61) | XICOR | SOP8W | 2007+ | SE: 1 W to 20 W; BTL: 4 W to 40 W operation possibility Soft clipping S |
| X77 | (2) | MOT | PLCC-28 | BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectiv | |
| X78 | (3) | XICOR | E302/E304 | SSOP-8 | The SiP5630 senses the operational state of the SCSI bus via the DIFFSEN |
| X79 | (11) | LQFN-16 | 02+/03+/04+ | Lamp Current Feedback Soft Start on Feedback Voltage Dimming (0V~2V) | |
| X7A | (1) | The DS1267 contains two 256-position potentiometers whose wiper positions | |||
| X7N | (1) | MOT | SOP | The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locke | |
| X7R | (15) | SMD | Ref input is 5V tolerant 4 pairs of programmable skew outputs Low skew: | ||
| X80 | (38) | XICOR | QFP | 04+ | The TPS758xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage v |
| X81 | (18) | 2008 | These synchronous, presettable counters feature an internal carry look ah | ||
| X82 | (88) | ST | 07+ | The DS1809 Dallastat is a nonvolatile digitally controlled potentiometer | |
| X83 | (6) | ETA | 05+ | 875 | The IRU1050 keeps a constant 1.25V between the out- put pin and the adjus |
| X84 | (69) | N/A | N/A | N/A | The DVR EN*, DATA, and VTT EN pins are digital inputs that control the dr |
| X85 | (1) | The 221 and LS221 devices are dual multivibrators with performance char | |||
| X86 | (13) | ST | 07+ | 1) Skew is defined as the absolute value of the difference between the ac | |
| X87 | (1) | 12 | ST | 02+ | This device is fully specified for live-insertion applications using Ioff |
| X88 | (16) | XICOR | CDIP | CDIP | High-Performance Crossbar Switch. A high-performance crossbar switch acts |
| X89 | (1) | N/A | 04+ | „ Up to 64 general-purpose I/O pins (shared with on-chip per | |
| X8H | (1) | N/A | N/A | N/A | The DTMF generator will output one of 16 standard tone pairs determined b |
| X8N | (1) | completion of update Separate battery pin 2 4V operation | |||
| X90 | (63) | XICOR | SOP-8 | 00+ | DESCRIPTION The 74V2T241 is an advanced high-speed CMOS DUAL BUS BUFFER |
| X91 | (96) | N/A | Intersil(Xicor) | 04+ | The manufacturer and device codes can be accessed by software or hardware |
| X92 | (474) | XICOR | 2008 | ||
| X93 | (597) | N/A | Intersil(Xicor) | 04+ | The tuning fork type quartz crystal provides ultimate in size, performan |
| X94 | (487) | XICOR | 2008 | The TLE 6225 G is a quad channel low-side switch with four power DMOS sta | |
| X95 | (128) | INTERSIL | DIP-8 | 0813+ | where ä is expressed in nanoseconds, LO is in microhenrys per unit |
| X96 | (18) | INTERSIL | TSSOP-14 | 06+ | Antenna (Input): High-impedance, internally ac coupled receiver input. C |
| X97 | (7) | ST | SSOP | Gain Bandwidth Product: 2 MHz (typ.) Supply Current: IQ = 170 µA | |
| X98 | (27) | INTERSIL | _____________ | 05+ | The resistor array is composed of 99 resistive ele- ments. Between each |
| X99 | (18) | XICOR | SOP-8 | 04+ | The built-in-back-to-back Zener diodes have specifically been designed to |
| X9C | (121) | XICOR | SOP-8 | 0051+ | Sleep mode. Applying a voltage greater than 2 V to the REF pin disables t |
| X9E | (1) | MOT | BGA | 99+ | 2.2 Grclerof precedence. In the avant of a conflict Mwaen the text |
| X9M | (1) | The 16-bit synchronization counter is the basis behind the transmitted | |||
| X9P | (1) | 1. Renesas Technology Corp. puts the maximum effort into making semicondu | |||
| X9T | (1) | xicor | These TTL encoders feature priority decoding of the inputs to ensure that | ||
| X9X | (2) | N/A | P&S | 04+ | Notes: (1) ISR-will operate down to no load with reduced specifications. |
| X-A | (1) | The APL5523 is a dual low dropout regulator with output1 with 3.3V/0.5A a | |||
| XA- | (1) | Disconnect the XA-12969 from power and PC. Remove the PIC microcontrolle | |||
| XA0 | (7) | T | 03+ | True clock of differential pair CPU outputs. These are current mode outp | |
| XA1 | (8) | DIP | The CY7C68310 implements a USB 2.0 bridge for all ATA/ATAPI-6 compliant m | ||
| XA2 | (18) | SHARP | QFP | 95 | NOTES 1. MAXIMUM ALIGNMENT DEVIATION BETWEEN LEADS NOT TO BE GREATER THA |
| XA3 | (6) | SHARP | BGA | 07+ | Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and |
| XA4 | (5) | SHARP | QFP | 97+ | n Single +3.0V operation n Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P f |
| XA5 | (4) | SHARP | QFP | 2000 | The low-side is composed of two IGBTs including rectifying diodes for each |
| XA8 | (2) | This low failure rate represents data collected from Maxims reliab | |||
| XAA | (33) | MOTOROLA | SOP | 9. VCC must be applied either coincidentally or before VPP and remo | |
| XAB | (12) | SMD | The 312 decoders are a series of CMOS LSIs for remote control system app | ||
| XAC | (9) | MOTOROLA | SOP | 2001 | Note 1: Absolute Maximum Ratings are those values beyond which the life |
| XAD | (3) | 1.1 Scope. This specification covers the performance requirements | |||
| XAG | (1) | xaGre200 | |||
| XAL | (2) | All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output opera | |||
| XAM | (1) | The AHCT574 devices are octal edge-triggered D-type flip-flops that featu | |||
| XAP | (4) | The Write-In-Progress (WIP) bit is a volatile, read only bit and indicat | |||
| XAR | (1) | Member of the Texas Instruments Widebus™ Family Ideal for Use in P | |||
| XAS | (2) | ST | 07+ | No external component required. Programmable output current control by E | |
| XAT | (2) | TTL/CMOS input select control signals for the PECL POUT0-POUT3 outputs. PS | |||
| XAX | (2) | MAXIM | DIP8 | DIP8 | DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Outp |
| XAZ | (1) | The BRT (Bias Resistor Transistor) contains a single transistor wi | |||
| X-B | (2) | NSYSTECH | 0351+ | TQFP | The operating speed of each receiver and transmitter can be selected in |
| XB0 | (5) | TSSOP | 03+ | AS6UA25616 Intelliwatt™ active power circuitry Industrial and comm | |
| XB1 | (10) | TOREX | 00+ | NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow | |
| XB2 | (15) | The Z893XX DSPs are optimized to accommodate ad- vanced signal processin | |||
| XB3 | (4) | TI | PLCC | Sensitivity: A magnetic south pole at and perpendicular to the device symb | |
| XB4 | (2) | When an acceleration is applied to the sensor the proof mass displaces fr | |||
| XB5 | (3) | MOT | 9436 | The standard device offers access times of 90, 100, 120, and 150 ns, al | |
| XB6 | (1) | XILINX | 1000 | 01+ | Proven in substantial volumes, this device and its fixed-frequency |
| XB9 | (1) | TQS | BGA | 05+ | Input/Output Capacitors: For proper operation in all applications, the PT |
| XBA | (4) | CP CLARE | DIP8 | 07+ | The ATA controller inside ADM uses DMA allowing instant data transfer f |
| XBB | (2) | CP CLARE | DIP8 | 07+ | Reliable CMOS with MNOS cell technology 105 erase/write cycles (in page m |
| XBC | (2) | SYNOPTICS | . | 16 | 1. Compact 8-pin DIP size The device comes in a compact (W) 6.4(L) 9.78 |
| XBG | (1) | 2 | Unless otherwise specified, the following specifications apply over the o | ||
| XBH | (1) | N/A | Also useful for RS-232 transceivers is the capability for switching betwe | ||
| XBI | (1) | Member of Texas Instruments Widebus Family OEC Circuitry | |||
| XBN | (1) | TI | 06+ | 1015 | Interfaces 8 E1/T1/J1 ports UTOPIA Interfaces (level 1 a |
| XBO | (8) | PH | 07+ | Transmitter Underrun: TxU is asserted during a transmit sequence when the | |
| XBP | (13) | Efficiency at 8-A Continuous Output Source or Sink Current Disabled Curr | |||
| XBR | (2) | NSYS | Calibrated directly in Kelvin Linear 10 mV/¡C scale f | ||
| XBS | (3) | XBS | 06+ | 7500 | The ADC12081 is a monolithic CMOS analog-to-digital con- verter capable |
| XBT | (1) | The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,07 | |||
| XBU | (1) | N/A | ALCATEL | 04+ | By driving the load differentially through outputs Vo1 and Vo2, an ampl |
| XBZ | (1) | ALTERA | n/a | n/a | This line of Schottky diodes is optimized for use in mixer appli- cation |
| XC- | (2) | XILINX | 06+ | TAOperating free-air temperatureC4085C NOTE 3: All unused inputs o | |
| XC/ | (6) | MOT | . | 300 | This document describes how to design a platform with a common footprint |
| XC0 | (35) | N/A | QFN40 | 06+ | • Any System Requiring RS-232 Communication Ports - Battery |
| XC1 | (1109) | MOTROLA | . | 6 | The thermal protection circuit shuts off the amplifier when the s |
| XC2 | (3241) | FXXC | 00+ | ! Available in a single mode (160-bits shift register) or in a dua | |
| XC3 | (3531) | XILINX | N/A | Short circuit protection is provided through foldback current limiting. | |
| XC4 | (5650) | XILINX | Since the 1996 model year, North American automobiles have been | ||
| XC5 | (1300) | XILINX | TQFP | 05+ | |
| XC6 | (4312) | TOREX | 98 | Notes: 1. For Max. or Min. conditions, use appropriate value specified u | |
| XC7 | (537) | XILINX | The MAX1973/MAX1974 are constant-frequency 1.4MHz pulse-width-modulated ( | ||
| XC8 | (78) | MOT | PGA | † All typical values are at VCC = 3.3 V, TA = 25C. ‡ For con | |
| XC9 | (2308) | TOREX In series stock | SOT25 | 2007 | The 70C version utilizes an industry standard line driver IC (26LS31) wh |
| XCA | (48) | N/A | DIP-6 | N/A | Information furnished is believed to be accurate and reliable. However, S |
| XCB | (18) | CP CLARE | . | The A0 to A6 inputs are used to specify which bytes within the page are t | |
| XCC | (33) | N/A | 1808 | NOTES: 1. All voltage values, except differential voltages, are with resp | |
| XCD | (26) | MOT | 95+ | QFP | C1 Commutation Capacitor Negative Terminal. C2 Commutation Capacitor Po |
| XCE | (49) | The evaluation board is useful for your design and to have more understand | |||
| XCF | (116) | XILINX | TSSOP | 02+ | TAOperating free-air temperatureC55125C4085C NOTE 3: All unused in |
| XCG | (1) | The LTC2439-1 accepts any external differential reference voltage from 0. | |||
| XCH | (3) | MOTOROLA | In voltage regulator applications where very large load cur- rents are p | ||
| XCI | (3) | QFP | XILINX | 04+ | VOLTAGE OUTPUT versus APPLIED DIFFERENTIAL PRESSURE The di |
| XCK | (6) | SONY | 97 | CAUTION: The BiCMOS inherent to the design of this component increases the | |
| XCL | (4) | Stresses beyond those listed under "Absolute Maximum Ratings" m | |||
| XCM | (70) | MOTOROLA | 06+ | QFN | • Floating Channel Designed For Bootstrapping Operation To |
| XCN | (2) | TI | 06+ | 590 | Reference level for the relative attenuation arel of the TFS 1220B is the |
| XCO | (1) | ||||
| XCP | (24) | MOT | BGA | N/A | Note that the level 7 interrupt is also level sensitive, and must be held |
| XCR | (691) | Xilinx | new | ||
| XCS | (839) | XC | 02+ | 1450 | Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive po |
| XCT | (7) | CREATIVE | PLCC68 | 05+ | The voltage at the threshold adjust pin (VTH.A) can be set with any volta |
| XCU | (3) | XILINX | 2. Turn-Off Energy Loss (EOFF) is defined as the integral of the in | ||
| XCV | (2227) | XILINX | SOP | 02+ | Features • Serial Input Bus • Two Squib Outputs • LowC a |
| XCW | (1) | Under the control of the output enable term, the I/O pin can function as | |||
| XCX | (1) | The IR 3310(S) is a Fully Protected 4 terminal high side switch. The inpu | |||
| XCY | (6) | TI | 00+ | TSSOP48 | These devices feature 3-state outputs designed specifically for driving h |
| XD0 | (2) | DIP | 00+ | The Microchip Technology Inc. 24AA32A/24LC32A (24XX32A*) is a 32 Kbit E | |
| XD1 | (21) | TI | QFP208 | The MAX7447 is designed to process S-Video and CVBS video signals. The vi | |
| XD2 | (3) | XICOR | The design is based on an ARM7® microprocessor that controls the enti | ||
| XD3 | (6) | The PCnet-ISA II Ethernet controller is part of the AMD PCnet family of | |||
| XD4 | (2) | YAMAHA | TQFP | N/A | The XD462 is a unipolar Hall effect sensor IC fab- ricated from mixed sig |
| XD5 | (1) | Information Input Regarding the Primary Current. The primary current rise | |||
| XD7 | (32) | 9 | DIP | 87 | For high-density packaging applications, the UCN5818EPF is furnish |
| XD8 | (2) | Large area diode chip for medium current photovoltaic by- pass applicat | |||
| XDA | (9) | EXEL(罗姆) | SOT-323 | 96+ | I 32-level Low Voltage Detection I Brown-out Reset I Software selectabl |
| XDC | (11) | ROHM | SOT23 | The USB descriptors and keyboard matrix can be customized via an optional | |
| XDD | (6) | N/A | BGA | 07+ | • High-speed, low-power, unidirectional, First-In First-Out |
| XDI | (1) | N/A | Stresses above those listed under Absolute Maximum Ratings may cause per | ||
| XDL | (3) | PARAMETER VCC Under-Voltage Lockout Start Threshold Stop Thresho | |||
| XDM | (3) | N/A | 98 | DIP40 | SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, |
| XDS | (2) | CAL | CAN | For optimal DSP program execution, programmers must follow the DSPs set | |
| XDT | (1) | MOTO | 04+ | ||
| XDU | (1) | SMD | 06+ | • Low Cost Infrared Data Link • Guaranteed to Meet IrDA &n | |
| XDV | (8) | 1000 | TI | Topic Section 1, Overview Section 2, Features Section 3, Maximum Tolera | |
| X-E | (1) | TI | SBGA | 01+ | The logic enable disables the power switch, the bias for the charge pump, |
| XE- | (2) | NISSAN | address, and I/O pins that permit independent, asynchronous access for re | ||
| XE0 | (2) | Abnormal voltage detecting voltage VBLT variation with supply voltage | |||
| XE1 | (28) | XECOM | NOTES (a) For a device surface mounted on 50mm x 50mm FR4 PCB with high | ||
| XE2 | (3) | XECOM | 模块 | 08+ | Fully compliant with USB v1.1 specification and USB Device Class Definiti |
| XE3 | (8) | SEMTECH | TSSOP-20 | 06+ | 2. Samsung products are not intended for use in life support, critical car |
| XE4 | (1) | CDIP | CDIP | The RC4700 incorporates a complete floating-point co-processor on | |
| XE5 | (1) | The two flip-flops in each IOB have a common clock enable input,which t | |||
| XE6 | (2) | Netgear | 2003 | Data Bus: DB07CDB00 contain bidirectional data while DB15CDB08 contain co | |
| XE7 | (2) | YAMAHA | DIP | 04+ | Output Buffer Amplifiers The voltage outputs are from precision unity-ga |
| XE8 | (9) | internal current-control circuitry (or by the PHASE or ENABLE inputs). | |||
| XE9 | (1) | USA | 178 | Setting up a password is done essentially in the same way as writing data | |
| XEA | (1) | MOT | DIP | Four 16-Bit CMOS ADC Input Ports Programmable Closed Loop VGA Control Wit | |
| XEB | (5) | ON | TSSOP | An inhibit function is provided for HR150 converters when the inhibit in | |
| XEC | (21) | N/A | 25201008 | ANALOG-TO-DIGITAL CONVERTER (including MUX and attenuators) Total | |
| XEL | (37) | The XEL01 is a monolithically integrated Digital Audio Broadcasting one-c | |||
| XEO | (71) | 3.7 Certificate of conformance. A certificate of conformance as re | |||
| XEP | (9) | MICREL | TQFP32 | 01+ | The SPT5230 voltage output will swing from +3.0 V to +4.99 V for VCS2 = |
| XER | (10) | ST | The evaluation board is useful for your design and to have more understand | ||
| XEY | (1) | 02+ | PLCC-44 | SDRAM Chip-select signal which is multiplexed with CS3 signal. These two | |
| X-F | (1) | 2008 | n Provides constant and proper gate drive to power MOSFETs regard | ||
| XF- | (2) | The product information and the selection guides facilitate selection of | |||
| XF0 | (26) | XFMRS | 00+ | SOP | Hardware data protection measures include a low V CC detector that autom |
| XF1 | (12) | XFMRS | 0412+ | Disclaimer: The contents of this document are subject to change without n | |
| XF2 | (117) | OMRON | 原装 | 08+ | n Input frequency range from 30 MHz to 95 MHz n Support display resolut |
| XF3 | (3) | Feedback Disable: This input controls the state of QFA[0:1]. When HIGH, t | |||
| XF4 | (5) | The FCT374T and FCT574T are high-speed low-power octal D-type flip | |||
| XF5 | (5) | MURata | 4532-后面12点 | 05+ | This document contains PRELIMINARY INFORMATION data. ISSI reserves the ri |
| XF6 | (9) | ST | SOP | 03+ | Load Regulation Since the IRU1010 is only a three-terminal device, it is |
| XF7 | (30) | TI | BGA | 98+ | (6) When designing your equipment, comply with the guaranteed values, in |
| XF8 | (3) | XFMRS | SMD | 97+ | • N channel FET switches with no parasitic diode to VCC C I |
| XF9 | (5) | Incorporates VDDQ, VTT Regulators Internal Switching Standby Regulator f | |||
| XFA | (19) | VICOR | (1) The DC specifications refer to the condition where the LVDS outputs a | ||
| XFB | (1) | To solve this problem, the DS1481 uses the busy signal issued during a | |||
| XFC | (11) | TQFP-M144P | 38503 | CONEXANT | VCCL, VCCR, VLC0L, VLC0R, VLC1L, VLC1R, VLC4L, VLC4R, VLC5L and VLC5R Re |
| XFD | (4) | Reading from the device is accomplished by taking Chip Enable (CE) and | |||
| XFE | (1) | I ARM720T Processor ARM7TDMI CPU 8 KB of four-way set-as | |||
| XFG | (1) | Calculation example (please refer to the parameter table above) Suppose t | |||
| XFI | (1) | N/A | Operation-PC Uses FA computer to display different kinds of settings, s | ||
| XFM | (3) | Input to the on-chip inverting oscillator amplifier To use the internal | |||
| XFN | (2) | *Note: In order to develop, make, use, or sell readers and/or other produc | |||
| XFP | (3) | fujikura | fujikura | dc96 | The MX93521 is fully controlled by a HOST controller through a simple HOS |
| XFQ | (1) | MOT | • Slope Analog-to-Digital (A/D) converter - Eight external | ||
| XFS | (4) | rating only, and functional operation of the device at these or any other | |||
| XFU | (1) | UL Recognized File # E-96005 Glass passivated junction | |||
| XFV | (4) | XFMRS | OPA63xUPin 8 disables the output when high (OPA632 and OPA635). Table VI | ||
| XFW | (3) | The HYM71V16M755HC(L)T8 Series are 16Mx72bits Synchronous DRAM Modules. Th | |||
| XG- | (1) | MOT | PLCC52 | 02/04+ | 1. Data patterns are to have maximum run lengths and DC balance shifts no |
| XG0 | (4) | CAN3 | MOT | 05+06+ | This product has been designed to meet the extreme test conditions and env |
| XG1 | (1) | ||||
| XG2 | (3) | Notes: 1. Unused inputs must be held high or low to prevent them from fl | |||
| XG3 | (21) | CHN | CAN | Thereareadditionalprovisionsfor demonstrating DDX-2000 functionality.The | |
| XG4 | (36) | CHN | CAN | The EL2244 and EL2444 also feature an extremely wide output voltage swi | |
| XG5 | (11) | FREESCALE | 0537+ | BGA | Fully compatible with 16550 and 16450 devices Enhanced UART mode Sharp- |
| XG8 | (4) | OMRON | 原装 | 08+ | When RESET goes active as a result of a low voltage condition or Watchd |
| XGA | (1) | The WB mode is similar to the FM mode, but to reduce the bandwidth the AM | |||
| XGC | (6) | Xilinx | new | Four of the nine instructions end with the transmission of the instructi | |
| XGF | (20) | CHN | CAN | Note 2: Absolute maximum ratings are those values beyond which damage to | |
| XGP | (8) | SYCHIP | BGA/25 | 02+ | The ADSP-21991 integrates the fixed point ADSP-219x family base architec |
| XGT | (2) | The PAL/NTSC pin determines the default values for the DVE control regist | |||
| XH0 | (13) | 00+ | Under and over temperature alert thresholds can be programmed to cause t | ||
| XH1 | (12) | ST | 01+ | SSOP | DESCRIPTION The XH11007920 is a 45-watt RF MOSFET Amplifier Modu |
| XH2 | (7) | DIP | 99+ | The MM54C151 multiplexer is a monolithic complementary MOS (CMOS) integra | |
| XH3 | (9) | XILINX | QFP | Provides up to 8K-Address Matching System Provides Glueless External-Add | |
| XH4 | (6) | SEIKO | N/A | The standard device offers access times of 70, 90, and 120 ns, allowing h | |
| XH5 | (3) | ST | TQFP44 | 00+ | The UCC281 series is specified for operation over the in- dustrial rang |
| XH7 | (1) | N/A | DIP | GND. Active-High Enable Input. A logic low reduces the supply current to | |
| XH9 | (1) | YAMAHA | The D 2Pak is a surface mount power package capable of accommodating di | ||
| XHA | (5) | TI | SSOP-16 | MaverickCrunch™ Math Engine • Floating point, integer and si | |
| XHB | (4) | TI | 00+ | Maximum terminal current is bounded by the maximum applied voltage | |
| XHC | (2) | DATAFAB | TQFP-M100P | 6+ | |
| XHE | (2) | The TSOP344..SB1F - series are miniaturized receiv- ers for infrared re | |||
| XHF | (2) | Colog | 08+ | Referring to the level detector block diagram of Figure 3, the RECIN inp | |
| XHI | (3) | INTERSIL | 00+ | 3P | |
| XHL | (7) | MOT | 模块 | 07+ | A simplified block diagram of the HPC3130A is provided below. The block d |
| XHP | (29) | mot | mot | dc95 | NOTES : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are |
| XHS | (4) | These are single-chip 16-bit microcomputers designed with high-per- form | |||
| XHT | (3) | MOT | SOP8 | 00+ | The XHT21 encodes incoming data into quad-bits represented by 16 possible |
| XHW | (18) | MOTOROLA | (LX)high-frequency | The MK3725 VCXO function consists of the external crystal and the integ | |
| XI- | (11) | N/A | Full advantage of the U.S. UL943 timing specification is taken to ensure | ||
| XI0 | (2) | Wrap Enable. This pin is active HIGH. When asserted, the high-speed serial | |||
| XI8 | (1) | YAMAHA | NOTES: 1. Dimensions are in inches. 2. Metric equivalents | ||
| XI9 | (2) | SHARP | DIP-54 | 02+ | VIN: Supplies the current to the collector of the output power transistor |
| XIC | (2) | XICOR | SOP-8 | 3 | Note 8: CIN, COUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors |
| XID | (3) | PLCC 28 | ESN (Electronic Serial Number), customer code (pro- grammed through AMD | ||
| XIE | (1) | ST | 00+ | 34 | NOTE: ESD data available upon request. 1. 10H circuits are designed to |
| XIF | (4) | 1000 | driven from internal selectable clock (oscillator or CPU cl | ||
| XIG | (1) | IXYS | 03+ | 247 | BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous ope |
| XIH | (1) | TAI TIEN | 046+ | This document contains information which is protected by copyright. All r | |
| XII | (1) | Vertical power TrenchMOS Low on-state resistance CMOS logic compatibl | |||
| XIL | (5) | • Bidirectional data strobe(DQS) • Differential clock inputs( | |||
| XIM | (3) | 10000 | 05+ | Note 4: For a power supply of 5V r10% the worst case output voltages (VOH | |
| XIO | (16) | TI | STK | 2007+ | NOTES: 1. Stresses beyond those listed may cause permanent damage to the |
| XIP | (1) | N/A | 05+ | The conditional skip is activated by instruction. Once the condition is | |
| XIR | (7) | BB | . | A 75 Ω termination resistor with short traces should be attached be | |
| XIT | (4) | CAL | CAN | The loop is stabilized by a PID compensation amplifier with high stabili | |
| XIV | (1) | TI | TSSOP-24 | Data Registers (DR3 to DR0) The potentiometer has four 10-bit non-volati | |
| XJ1 | (2) | MPD | 高频管 | N/A | Figure 2 shows the recovered clock (RCLK), positive data (RPOS) and negat |
| XJ3 | (1) | YAMAHA | † Signaling rate by TIA/EIA-485-A definition restrict transition ti | ||
| XJ6 | (1) | The LM3200 offers superior features and performance for mobile phones a | |||
| XJ8 | (5) | YAMAHA | QFP | 99 | Propagation Delay Tempco Prop Delay SkewRising Transition to Fal |
| XJ9 | (3) | QFP | 91 | STR73xF family combines the high performance ARM7TDMI™ CPU with an | |
| XJD | (1) | Drain-to-Source Breakdown Voltage Gate Threshold Voltage Ga | |||
| XJH | (3) | Note 17: This describes the difference between the delay of the LOW-to-HIG | |||
| XJT | (1) | ABA-31563 is fabricated using Agilents HP25 silicon bipolar process, whi | |||
| XK1 | (3) | NS | PQFP-144 | 01 | The SN74ALVCF162835 has series damping resistors in the device output s |
| XK3 | (2) | 876 | OCx is an output signal that is asserted (active low) when an overcurrent | ||
| XK4 | (1) | N/A | sanyo | 05+ | Notes: (i) See Safe Operating Area curves or contact the factory for the |
| XK5 | (2) | YAMAHA | The XK591BO is a switched capacitor voltage inverter that produces a ne | ||
| XK6 | (1) | The device pins also have the ability to set outputs to fixed HIGH or L | |||
| XK7 | (2) | The tuning input is typically connected to the output of the PLL loop fil | |||
| XKA | (2) | The SK-2910 Series of quartz crystal oscillators provide DPECL Fast Edge | |||
| XKS | (1) | The AGU is divided into two halves, each with its own Address ALU. Each A | |||
| XKT | (4) | ON | 02+ | SOP-8 | The IS41C4100 and IS41LV4100 is a CMOS DRAM optimized for high-speed ba |
| XL- | (10) | TEITEK | SOP | The receiver section of the WE904/905 provide all of the required receiver | |
| XL0 | (6) | MAX | SMD | OO | Note 1: Absolute Maximum Ratings are those values beyond which the life |
| XL1 | (16) | NA | 02+ | SOP8 | DESCRIPTION The 74VHCT03A is an advanced high-speed CMOS QUAD 2-INPUT |
| XL2 | (17) | N/A | SOP | 06+ | For the purposes of simplification, the following descrip- tions will ass |
| XL3 | (9) | SANYO | 16-Bit Monotonic Over Temperature Relative Accuracy: 8 LSB (Max) Glitch | ||
| XL4 | (1) | - | SSOP20 | 07+/08+ | The UPC2721 output amplifier is a single-end push-pull ampli- fier desig |
| XL5 | (1) | MOSEL | DIP | 92 | Up to 630 Mbps Simplex (Point-to-Point) and Half-Duplex (Multipoint) Int |
| XL6 | (3) | SANYO | MODULE | USB data is a 3.3-V level signal, but power is distributed at 5 V to allo | |
| XL7 | (1) | Note 1: The deviation parameters, Vref(dev) and Iref(dev) are defined as | |||
| XL8 | (11) | WEITEK | 92+ | PGA | 5. Applies to each output; each output has independent thermal shutdown; |
| XL9 | (31) | exel | exel | dc94 | CML outputs have a common-mode voltage near VCC. To avoid changing this o |
| XLA | (37) | SSOP24 | 2007+ | High Power Switching Regulator Controller for DDR Memory Termination VOU | |
| XLB | (10) | ||||
| XLC | (4) | XIRLINK | PLCC-44 | 96+ | Enhanced N channel FET with no inherent diode to Vcc 16:8 multiplexer fu |
| XLE | (7) | EXEL | 2007 | With the Hold input held High - Figure 4. As frequencies are inpu | |
| XLF | (3) | The XLF4G20S-110/XLF4G20S-110 are microprocessor (µP) supervisory c | |||
| XLH | (3) | N/A | QFP | 07+ | Like all members of the FLASH370i family, the CY7C372i is rich in I/O res |
| XLJ | (15) | EXEL | 486 | 9526 | The XR16C854/854D1 (854) is an enhanced quad Universal Asynchronous Rec |
| XLM | (3) | TEXAS | SO-14 | 04+ | LED PULSE The 9Cvolt battery level is checked every 40 seconds du |
| XLN | (1) | The XLN8P15SP consists of a high-voltage circuit, optically coupled w | |||
| XLP | (3) | *Absolute Maximum Ratings are those values beyond which damage to the dev | |||
| XLR | (5) | When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on | |||
| XLS | (90) | exel | exel | dc87 | Sirenza Microdevices SBB-2089 is a high performance InGaP HBT MMIC amplif |
| XLT | (27) | TMIN = −40C, and TMAX = +85C. Typical values are at TA = 25C, clock | |||
| XLU | (23) | ROHM | The MSM7718, developed for PHS (Personal Handyphone System) applications, | ||
| XLV | (16) | SOP14 | (14) Interrupts: 21-source, 10-vectored interrupts 1) Three prior | ||
| XLW | (4) | TEXAS | SSOP | 99+ | Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Volta |
| XLX | (2) | The P82B96 offers many different ways in which it can be used as a bus i | |||
| XM- | (6) | Typ, min, and max values at TA = 25C, full temperature range is TMIN = &# | |||
| XM0 | (3) | XM | QFP0909-44 | 01+ | Optional accessories for modules Keyed gate/cathode twin plugs with wir |
| XM1 | (9) | XM | 06+ | 500 | Rail-to-rail input and output voltage ranges 5.0V/µs slew rate O |
| XM2 | (22) | YAMAHA | PQFP64 | Stresses beyond those listed under Absolute Maximum Ratings may cause perm | |
| XM3 | (15) | ST | DIP20 | Bay Linear products are not authorized for and should not be used within | |
| XM4 | (3) | BGA | These phase detector outputs can be combined externally for a loo | ||
| XM5 | (8) | Murata | 05+ | QFN | Synchronous Parallel Input/Serial Output (MC14014B) Asynch |
| XM6 | (3) | PLCC | In normal mode (LPWR = 0, MCLK = 2.048 MHz), power consumption is 25 mW | ||
| XM8 | (2) | 01 | The AV9155 is a low cost frequency generator designed spe- cifically for | ||
| XM9 | (2) | XM | 00+ | QFP0909-44 | Other brands and names are the property of their respective owners |
| XMA | (1) | ST | QFP-48 | This IC is a sync detection circuit for obtaining the best reception state | |
| XMB | (2) | MALAYSIA | SOT-323 | 05+ | • Microcontroller support; only for control, no specific des |
| XMC | (7) | MOTOROLA | O7+ | AMDs Flash technology combines years of Flash memory manufacturing expe | |
| XMF | (5) | 08+ | • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V p | ||
| XMM | (2) | mot | mot | dc9736 | (1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle 10%. *Measurement mad |
| XMO | (2) | 99+ | 1700 | The MAX6501/MAX6503 have an active-low, open-drain output intended to int | |
| XMR | (1) | ||||
| XMS | (5) | TI | PGA121 | 杂 | † Stresses beyond those listed under absolute maximum ratings may c |
| XMT | (4) | NOTE: 1. AVSS (reference ground) must be connected to 0V (ground). AVCC | |||
| XMZ | (1) | PHILIPS | SOP08 | 07+ | Once triggered, the output pulse width may be extended by retriggering |
| XN0 | (36) | PAN | SOT-153 | Signal integrity is crucial in high-speed digital designs because of inc | |
| XN1 | (113) | Panasonic | |||
| XN2 | (17) | Panasonic | SOT-153 | 05+ | VDD: The power input connection for this device. Although quiescent VDD c |
| XN3 | (2) | MOT | Notes: 1. For Max. or Min. conditions, use appropriate value specified un | ||
| XN4 | (122) | PANASONIC | SMD | 2008 | This pin is connected to the 12 V supply and serves as the power Vcc pin |
| XN5 | (18) | YAMAHA | In Loopback mode Only one output drive pin per package will be shorted | ||
| XN6 | (47) | PAN | SOT-223-6P | 1998 | The W83877TF is an enhanced version from Winbond's most popular I/O chip |
| XN7 | (2) | PAN | SOT-163 | 05+ | The XN7651 provides a 5V (typ.) fixed voltage to drive a Flash LED with |
| XNC | (1) | The transmit section of the CY7B951 contains a PLL that takes a REFCLK i | |||
| XND | (1) | 99 | • Universal digital interface accepts YCrCb (CCIR601 or 656 | ||
| XNE | (1) | TI | 02+ | 大SOP-8 | Notes: 1: Stresses above those listed in Absolute Maximum Ratings may cau |
| XNM | (10) | Because the PMOS device behaves as a low-value resistor, the dropout volt | |||
| XNO | (4) | PAN | SOT-23-6 | Excellent ac characteristics, such as 20MHz GBW, 30V/µs slew rate | |
| XO- | (42) | DL | 06+/07+ | ||
| XO0 | (2) | Unit-to-Unit Propagation Delay Skew POWER SUPPLY Positive | |||
| XO1 | (5) | NULL | 07+ | Day of the Week Register (DW) This register provides a Day of the Week s | |
| XO2 | (2) | XILINX | 1450 | ||
| XO3 | (7) | TAG | CAN3 | 00+ | Parameter VDD to GND VA, VB, VW to GND PU, PD, PRE Voltage to GND Maxi |
| XO4 | (6) | ST | TO-220 | 05+ | In the IF section, it can be selected if the first IF signal is down-conv |
| XO5 | (14) | SHARP | . | 4 | Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2CTM serial b |
| XO6 | (1) | Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Volta | |||
| XO7 | (4) | SHARP | . | 2 | |
| XO8 | (2) | ST | TO-220 | DESCRIPTION This Power Mosfet is the latest development of STMicroelect | |
| XO9 | (2) | DIP20 | 38503 | SHARP | |
| XOE | (1) | ||||
| XOG | (7) | KDS | SMD | 07+/08+ | Broad Support Program: A BSP layer is provided to allow easy porting of p |
| XOM | (8) | TI | BGA | Two Pulse Width Modulator modules each with six PWM outputs, three Curren | |
| XON | (1) | IC. Each display can be directly interfaced with a microprocessor, thu | |||
| XOS | (9) | MINI | 02+ | Valid Combinations Valid Combinations list configurations planne | |
| X-P | (3) | SEAGATE | 2003 | PQFP | push-pull outputs which are sequentially pulsed in groupings of bursts; a |
| XP- | (7) | VICOR | stock | The chip enable-controlled access is initiated by CE going active while | |
| XP0 | (105) | Panasonic | 02+ | The Rambus Direct RDRAM™ is a general purpose high-performance memo | |
| XP1 | (184) | Panasonic | SOT-353 | 04+ | |
| XP2 | (43) | 04+ | To measure the performance of the sensor in the module, a sensor test mod | ||
| XP3 | (11) | Panasonic | SOT-353 | 05+ | Notes) • The 64-bit slot is an LSB first, two's complement output, |
| XP4 | (83) | Panasonic | SOT-363 | 05+ | The AGU performs the effective address calculations using integer arithme |
| XP5 | (17) | PANASONIC | SOT-363 | The ballast control section is built around the IR21592 Dimming Ballast C | |
| XP6 | (50) | 98 | DIP-18 | Under-Voltage Lockout An Under-Voltage Lock-Out (UVLO) inhibits the ope | |
| XP7 | (3) | YAMAHA | DIP-64 | The Hynix HYM76V8655HGT8 Series are 8Mx64bits Synchronous DRAM Modules. Th | |
| XP8 | (11) | XP | PLCC | 9835+ | NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATI |
| XPA | (7) | N/A | QFP | JEDEC standard 3.3V power supply LVTTL compatible with multip | |
| XPC | (965) | MOTOROLA | BGA | 06+ | The PowerInfo 2 board facilitates serial or USB com- munication between |
| XPE | (3) | MOT | CBGA | N/A | The receiver includes a half wave rectifier that rectifies the analog si |
| XPF | (6) | SOP24 | The QS32X2245 provides a set of 16 high-speed CMOS TTL-compatible | ||
| XPG | (1) | NS | 06+ | 1000 | Discription Data bit 0 of Transmit Symbol, true data Data bit 1 of Tra |
| XPI | (14) | AMCC | BGA | VDD: Chip power supply pin. VDD should be bypassed to PGND. The C1 and C | |
| XPL | (4) | MOTOROLA | 78 | † Stresses beyond those listed under absolute maximum ratings may c | |
| XPM | (1) | MOT | SIP-12 | 1 | When VCC is between 0 and 1.2 V, the device is in the high-impedance stat |
| XPN | (1) | AMI | TQFP1414-100 | 99+/00+ | The IC must be equipped with external RC circuitry to limit the voltage i |
| XPO | (6) | PAN | SOT-363 | • 0.23 µm Process Technology • Single 3.0 V read, progr | |
| XPR | (1) | ATI | BGA | 06+ | Constructed with the Intersil dielectrically isolated Rad Hard Silicon G |
| XPS | (4) | MOT | 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed dev | ||
| XPT | (13) | XPT | MSOP8 | 07+ | • N channel FET switches with no parasitic diode to VCC C I |
| XPV | (2) | BGA | The MAX1540/MAX1541 dual pulse-width modulation (PWM) controllers provide | ||
| XPX | (11) | HONEYWELL | The CD4512BC buffered 8-channel data selector is a com- plementary MOS | ||
| XPY | (1) | AMD is a trademark of Advanced Micro Devices, Inc. Award is a trademark | |||
| XPZ | (1) | The first character of the part number suffix determines the devic | |||
| XQ0 | (1) | 96 | Wichtige Hinweise! Mit den Angaben werden die Bauelemente spezifiziert, | ||
| XQ1 | (13) | N/A | N/A | N/A | PARAMETER Collector-emitter voltage peak value Collector-emitter voltage |
| XQ2 | (10) | HIT | SMD | 03+ | Notes: 1. These displays are recommended for high ambient light operatio |
| XQ4 | (131) | XILINX | 07+ | ||
| XQ6 | (1) | 48 | YAMAHA | 99+ | Notes: 1. For Max. or Min. conditions, use appropriate value specified u |
| XQ8 | (2) | YAMAHA | BYTE ENABLE: BYTE low places device x8 mode. All data is then input or ou | ||
| XQF | (1) | ||||
| XQR | (17) | XILINX | 07+ | Pin 10 POWER GROUND Ground for the output buffer supply Pins 11 thru 13 | |
| XQS | (1) | When the BLANKING input is high, the output source drivers are di | |||
| XQV | (104) | ?XILINX | ?BGA | ?08+ | This access is initiated when the following conditions are satisfied at c |
| X-R | (4) | AGERE | 01+ | Bild / Fig. 6 B6 - Sechpuls-Brckenschaltung / Six-pulse bridge circuit H | |
| XR- | (37) | 00+ | • Low On-Resistance (16Ω typ) Minimizes Distortion an | ||
| XR0 | (20) | 95 | The DS1258 devices execute a write cycle whenever WE and either/both of CE | ||
| XR1 | (274) | EXAR | 06+ | 3000 | CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic ch |
| XR2 | (208) | XR | DIP | The MSK 0002 is a general purpose current amplifier. It is the ind | |
| XR3 | (38) | EXAR | The HY51V(S)16403HG/HGL is the new generation dynamic RAM organized 4,194, | ||
| XR4 | (29) | EXAR | BGA | 0638+ | VBUS Pulsing: USB20H04 will drive VBUS long enough to cause the capacitan |
| XR5 | (54) | EXAR | DIP-8陶 | 8407 | A default serial loader program in the Boot ROM allows In-System Program |
| XR6 | (44) | XR | 2005 | The LPV511 is a micropower operational amplifier that op- erates from a | |
| XR7 | (3) | YAMAHA | DIP64 | 97+ | Each Peppermint board has a special touch pad built onto it that functio |
| XR8 | (65) | XR | This device is designed with discrete diodes for complete isolation. Each | ||
| XR9 | (4) | N/A | N/A | N/A | Small current step size Rise and Fall time will be determined by the Bandw |
| XRA | (83) | TQFP32 | 2007+ | Signal Processor (DSP) C SMJ320C62x C 5-ns Instruction Cycle Time | |
| XRC | (88) | Note 2: Unless otherwise specified, these specifications apply for temper | |||
| XRD | (67) | EXAR | QFP | As the beams attached to the central mass move, the distance from | |
| XRE | (13) | 08+ | operation essentially is zero, beyond the time needed for the serial pr | ||
| XRF | (92) | MOT | 高频管 | N/A | (VCC = +2.97V to +3.63V, CML output load is 50Ω to VCC, TA = -40C to |
| XRG | (2) | COSEL | North America Literature Fulfillment: Literature Distribution Center for | ||
| XRI | (1) | ST | BGA | N/A | In addition to increased performance and FIFO size, the OXCF950 also pro |
| XRJ | (4) | The OPA860 is a versatile monolithic component designed for wide-bandwi | |||
| XRK | (25) | XR | PLCC-32P | 04+ | Input Termination Center-Tap: Each side of the differential input pair te |
| XRL | (6) | EXAR | DIP-8 | 93+ | The real time clock keeps time in 1/256 second incre- ments. This can b |
| XRM | (11) | ROHM | 06+ | 129000 | This document is a general product description and is subject to change wi |
| XRN | (1) | The MAX1642/MAX1643 are high-efficiency, low-voltage, step-up DC-DC conve | |||
| XRO | (2) | ST | SOP14 | Negative Input Terminal Positive Input Terminal Positive Remote sense N | |
| XRP | (1) | DIP | Low cost, general duty, non-environmental MIL-C-5015 type connectors. Ava | ||
| XRQ | (8) | EXAR | The ST7263 Microcontrollers form a sub family of the ST7 dedicated to U | ||
| XRS | (6) | XR | The DEM-OPA68xU demonstration board is an unpopulated printed circuit b | ||
| XRT | (376) | XR | BOOST (Pin 1): Topside (Boosted) Driver Supply. This pin is used to boots | ||
| XRU | (53) | ROHM | . | 25 | The 33996 is a 16-output low-side switch with a 24-bit serial inpu |
| X-S | (2) | 95 | DIP-28 | The MBRS320TRPbF surface-mount Schottky rectifier has been designed for a | |
| XS/ | (1) | Pin Function PWM block control power supply Focus control inpu | |||
| XS0 | (2) | NS | Watchdog Adjustable Over- and Undervoltage Detection of Vcc = 5 V Standb | ||
| XS1 | (26) | xil | xil | dc02 | This series is designed with discrete diodes for complete isolation. Each |
| XS2 | (9) | ST | SMD 14 | 07+ | Since the MSK 610 is a high voltage amplifier, it is com- monly u |
| XS3 | (4) | YAMAHA | QFP-80 | 99+ | The 5002C is an audio/video switching device. The device integrates both |
| XS4 | (3) | ST | 01+ | 211 | |
| XS5 | (1) | 24 | YAMAHA | 98+ | A simple LC noise reduction filter (L5 and C7) is connected between pin |
| XS6 | (4) | TOREX | 05++ | SOT89 | This applies to SAA7120 only. The device is protected by USA patent num |
| XS7 | (4) | YAMAHA | 06+ | 500 | Some tests require the use of high voltages. After the device is mounted |
| XS8 | (12) | GENNUM | QFP | 04+ | Buffer memory address Buffer memory address Buffer memory address Bu |
| XS9 | (12) | GEM | O7+ | Cycle-by-cycle current limiting prevents the primary current from reachin | |
| XSA | (2) | The following specifications apply for VIN= 14V; VSHUTDOWN = Open; ILOAD | |||
| XSB | (1) | 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times | |||
| XSC | (12) | MOT | BGA | N/A | The contents of the offset registers can be read to the data outputs whe |
| XSD | (25) | CAL | CAN | Specifications to -40C are guaranteed by design and not production tested. | |
| XSF | (3) | Each LOW-to-HIGH transition on the Clock (CP) input shifts data one pla | |||
| XSH | (2) | ST | 99+ | 100 | Parameter Total Gate Charge (turn-on) Gate - Emitter Charge (t |
| XSI | (2) | N/A | ST | 04+ | (5) When designing your equipment, comply with the range of absolute maxi |
| XSM | (1) | 1. Permanent device damage may occur if Absolute Maximum Ratings are exce | |||
| XSN | (14) | TEXAS | 0736+ | • Power supply : Vdd: 2.5V 0.2V, Vddq: 2.5V 0.2V • Double-d | |
| XSO | (1) | The MI-MV13 is a 1,280H x 1,024V (1.3 megapixel) CMOS digital ima | |||
| XSP | (23) | N/A | N/A | N/A | This is the timing reference frequency which is the transmit frequency d |
| XSS | (3) | CAL | CAN | The signal current at the input flows into the summing node of a high-gai | |
| XST | (89) | STM | DIP-56 | 97+ | Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and |
| X-T | (20) | SUNTEL | 02+ | In MX98715A, an innovative and proprietary design "Adaptive Networ | |
| XT- | (2) | XIN-TEC | 07+ | Timing is measured at pin threshold, with 50 pF external capacitive loads | |
| XT0 | (14) | ST | 99+ | 95 | Chip Enable Input. If logic high, all functions are enabled. If logic low, |
| XT1 | (11) | CAL | CAN | The CX65105 is internally matched for optimum linearity and efficiency. T | |
| XT2 | (10) | ST | SOP16 | (6) Output Driver Control Function By setting HALTB pin to L, hig | |
| XT3 | (10) | YAMAHA | SOP44 | The XT354A0FPN/AFTN is a 4,194,304-bit static random access memory | |
| XT4 | (16) | 91 | The APW7004 provides a complete control and mul- tiple protection for a D | ||
| XT5 | (21) | 晶振 | |||
| XT6 | (2) | N/A | SOP | 06+ | Note 1 Absolute maximum ratings are those values beyond which damage to |
| XT7 | (12) | MOTOROLA | BGA | 2002 | The VP5313/VP5513 converts digital Y Cr Cb data into analog PAL |
| XT9 | (2) | XINTECH | 235 | PLCC44 | s GENERAL DESCRIPTION The NJM2171A is a low voltage headphone amp |
| XTA | (120) | ST | SSOP | Undershoot Clamp Diodes Low Power Consumption (ICC = 0.6 mA Typical) VC | |
| XTB | (1) | An output capacitor is required to maintain regulator loop stability. Un | |||
| XTC | (1) | MOTOROLA | 05+ | BGA | Stresses beyond those listed under "absolute maximum ratings" m |
| XTD | (5) | ST | BGA | 99 | The integrated high performance USB transceivers allow the ISP1563 to han |
| XTE | (3) | ST | 00+ | Amplifier input impedance is very high, requiring less than 1 pA of inp | |
| XTI | (4) | QFP | This text is here in white to force landscape pages to be rotated correct | ||
| XTJ | (1) | • 2.7VC3.6V operation • CMOS for optimum speed/power • | |||
| XTL | (24) | KSS | 04+ | • Microcontroller support; only for control, no specific des | |
| XTM | (4) | ST | PQFP | FEATURES Output Frequency Range: 1800 MHz to 2150 MHz Divide-by-2 outpu | |
| XTN | (18) | TI | BGA | 04+ | The XC5200 family provides a flexible coupling of logic and local routin |
| XTO | (1) | Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /C | |||
| XTP | (9) | TI | 07+ | The QS3V245 is an 8-bit high speed bus switch controlled by LVTTL- | |
| XTR | (137) | ST | DIP48 | DESCRIPTION These dual channel diode-transistor optocouple | |
| XTS | (4) | 00+ | Notes: 1. R1 is used to optimize the performance of the 870 nm LED, whil | ||
| XTV | (1) | IC | SOP | Typical DAC matching is 0.7 LSB across all codes. Accuracy of +0. | |
| XTW | (6) | TI | 99+ | BGA | Although the chip permits all combinations of encoding and modulation s |
| XTX | (1) | ST | QFP | 99+ | Performance warranty of products offered on this data sheet is limited to |
| XTY | (1) | Table 2 lists the A1 and A0 bits and the selection of the updated DACs. T | |||
| XU0 | (2) | Packaged in a small, 40-pin, ceramic TDIP, the functionally complete ADS | |||
| XU2 | (5) | CAL | CAN | 1. Hitachi neither warrants nor grants licenses of any rights of Hitachis | |
| XU3 | (11) | CAL | CAN | q ACTIVE 18-Line TERMINATOR q 2pF CAPACITANCE PER LINE IMPORTANT | |
| XU4 | (14) | CAL | CAN | ||
| XU5 | (1) | YAMAHA | 98+ | QFP1420-100 | NEC's NE663M04 is fabricated using NEC's UHS0 25 GHz fT wafer process. |
| XU7 | (5) | YAMAHA | DIP-64 | 00+ | Digital Filter, DAC and Analog Low-Pass Filter Blocks • Digital de |
| XU8 | (1) | YAMAHA | 2008 | In the normal mode, these devices are functionally equivalent to the F244 | |
| XU9 | (2) | YAMAHA | QFP | 98+ | The device is manufactured using Atmels high-density CMOS technology. By |
| XUA | (3) | ST | DIP | 07+ | The Bay Linear B3800 series is monolithic control circuit containing th |
| XUC | (1) | ||||
| XUL | (2) | Designed specifically for use in 3.3V microcomputers, this IC contains t | |||
| XUM | (2) | XUM | DIP | Hynix HYMD216646(L)6-K/H/L series is designed for high speed of up to 133M | |
| XUS | (1) | via an RF or an infrared transmission medium upon receipt of a trigger | |||
| XUZ | (2) | IC | SOP | 01+ | The scaled-down output voltage is internally monitored and a power good |
| X-V | (1) | Must be chosen from an inspection lot that has been submitted to and pass | |||
| XV- | (1) | CP: This is the input for the charge pump. For applications requiring a c | |||
| XV0 | (9) | 0805L | For more detailed information on cabling options including RS485, transfo | ||
| XV1 | (9) | IIXINC | 06+ | 2 channel 8-bit timer/counter operation (independent operation clocks for | |
| XV2 | (1) | YAMAHA | QFP | 99+ | tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setu |
| XV3 | (2) | advantage series | ＱＦＰ | original stock | Serial Mode Operation Three CMOS compatible signals control the attenuato |
| XV4 | (2) | YAMAHA | 99+ | DIP | CUSTOM). Zero suppression can exceed 100% of the input range. This enabl |
| XV5 | (2) | YAMAHA | SOP44 | Up to eight devices (two for the MSOP package) may be connected to the | |
| XV6 | (4) | 113 | YAMAHA | 99+ | AfT = exp((Ea/k)*(1/Tu - 1/Ts)) = tu/ts AfT = Acceleration factor due to |
| XV7 | (15) | ST | 03+ | 3500 | PARAMETER Error Comparator Section Input Bias Current Input Offset Volt |
| XV9 | (4) | 3376 | YAMAHA | 99+ | IF-Compensation Demodulator Chrominance Filter Frequency Demodulator |
| XVB | (1) | ||||
| XVC | (1) | XILINX | 02+ | BGA3535 | Note 3 The HALT mode will stop CKI from oscillating in the RC and crystal |
| XVM | (3) | QFP | VM | For the device-specific interrupt priority configurations, see the " | |
| XVN | (1) | ST | SMD-10 | 9748+ | L0, L1, L2Low-End Terminals of the Potentiometers. It is not required that |
| XVR | (2) | ||||
| XVS | (2) | XILINS QFP | Motorola reserves the right to make changes without further notice to any | ||
| XVT | (1) | MOT | SOP8 | This series of optically coupled isolators consist of a Gallium Arsenid | |
| X-W | (1) | ENOVA | 05+ | ||
| XW1 | (5) | YAMAHA | 99 | If the user wants to program the board with a file that is not the curre | |
| XW2 | (7) | The information provided herein is believed to be reliable at press time. | |||
| XW3 | (1) | fixed off-time. CT also sets the BLANK time (see the section App | |||
| XW4 | (2) | TOSHIBA | SOP | 00+ | RL/VL. The low (VL/RL) terminals of the X9C102/103/104/503 are equivalent |
| XW5 | (1) | YAMAHA | QFP | 07+ | • HIGH-DENSITY PROGRAMMABLE LOGIC 8000 PLD Gates 9 |
| XW7 | (1) | YAMAHA | QFP | 01+Original | Offerings include ball grid array (BGA) packages with 0.80 mm, 1.00 mm, |
| XW8 | (2) | YAMAHA | CLKBs output originates from the cross point switch and goes through a pr | ||
| XWA | (1) | TAITIEN ELECTRONICS | 0613+ | The DS1249 devices execute a read cycle whenever WE (Write Enable) is in | |
| XWC | (4) | The SY88713V generates a PECL SD output. A programmable signal-d | |||
| XWD | (6) | USA | PLCC | 97+ | Removed 166MHz part from speed bin Defined IDD specificati |
| XWF | (2) | ST | 99+ | 2207 | Advanced HEXFET ® Power MOSFETs from International Rectifier utiliz |
| XWH | (1) | TAITIEN ELECTRONICS | 0613+ | Electrical These devices use a modified 4 x 7 dot matrix of light emit | |
| XWM | (67) | WM | PLCC | 84 dB dynamic range TX/RX Integrated analog front end (AFE) and 2- to 4- | |
| XWR | (1) | C | 06+ | 2000 | When the JTAG interface in MAX 7000S devices is used for either boundary- |
| XWS | (6) | Notes: 1. Insulation characteristics are guaranteed only within the safet | |||
| XWT | (1) | HS Data; high-speed data output, outputting entire transport packets, p | |||
| XX- | (2) | MX | SOP44W | 2007+ | Vcc = 2.3V~2.7V, TA = 0C to 70C, unless otherwise specified -12 |
| XX0 | (1) | Note 1: Absolute Maximum Ratings are those values beyond which the life | |||
| XX1 | (26) | 94 | In applications where only mono 100W / 4Ω operation is desired, e.g | ||
| XX2 | (2) | NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS | |||
| XX3 | (1) | XEMICS | 01+ | • TOSHIBA is continually working to improve the quality and reliabil | |
| XX8 | (2) | EAIA | SOP-8P | 05+ | Overcharge detection output pin NPN transistor open collector output; nor |
| XXA | (11) | CP clare | SMD | SMD | A logic low on the CHIP ENABLE input will prevent the drivers fr |
| XXE | (1) | Vdd=2.7V~3.3V, TA = 0C to 70C(C) / -25C to 85C(E), unless otherwise specif | |||
| XXI | (2) | SHARP | 722 | HR300 converters use a constant frequency pulse-width modulated switchin | |
| XXL | (1) | This document is a general product description and is subject to change wi | |||
| XXP | (1) | N/A | PLCC-28 | The A-to-B enable (CEAB) input must be low to enter data from A or to o | |
| XXT | (3) | This IC functions in a variety of CPU systems and other logic systems to | |||
| XXV | (1) | XILINX | BGA | N/A | The MCS 96 microcontroller family members are all high-performance microc |
| XY- | (3) | When VCC is greater than 1V and less than the UVLO threshold, REF is pu | |||
| XY1 | (5) | YAMAHA | SOP44 | 00+ | MII Receive Data. Data is transferred from the INT5130 to the external M |
| XY2 | (4) | YAMAHA | SOP44 | 99+ | The LTC®6900 is a precision, low power oscillator that is easy to us |
| XY3 | (27) | Power-on reset LCD bias generator LCD voltage selector LCD drive mode | |||
| XY4 | (5) | MOT | SOP24 | 02+ | The ABT162244 devices are 16-bit buffers and line drivers designed spec |
| XY5 | (1) | YAMAHA | 9947 | DIP42 | Random Access Read Selective READ operations allow the Master device to |
| XY6 | (3) | YAMAHA | SOP44 | 00+ | The LM135, LM235, LM335 are precision tempera- ture sensors which can b |
| XY9 | (15) | 05+▲▲ | SMD | to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are | |
| XYA | (2) | ||||
| XYL | (12) | The MAX1698 features digital soft-start and adjustable lossless LED curre | |||
| XYW | (2) | charged with a constant current, I, until the upper switch- ing threshol | |||
| XYZ | (1) | FEATURES Clickless Bilateral Audio Switching Guaranteed Break-Before-Mak | |||
| XZ0 | (3) | SANYO | 2008 | The HYM72V32C736B(L)T8 Series are Dual In-line Memory Modules suita | |
| XZ1 | (6) | YAMAHA | QFP | 02+Original | The output signal is adjustable between 0.5V and 4.5V (when operating with |
| XZ3 | (1) | Power down protection is provided on all inputs and 0 to 7V can be acce | |||
| XZ5 | (3) | YAMAHA | QFP-80 | 01+ | The XZ547BO-104 is a high-speed triple 8-bit monolithic analog-to-digital |
| XZ7 | (6) | YAMAHA | SOP44 | Stresses above those listed under "Absolute Maximum Ratings" ma | |
| XZ8 | (1) | This device is ideal for applications requiring level translation. When | |||
| XZ9 | (2) | YAMAHA | O7+ | The SCSI bus DIFSENS signal line is used to identify which types of SCS | |
| XZB | (1) | Recovered Clock. These ECL 100K outputs (+5V referenced) represent the re | |||
| XZC | (2) | TOREX | 2008 | The write cycle is the time from a valid stop condition of a write sequen | |
| XZH | (1) | ZETEX | 05+ | Magnitude of Common Emitter Small-Signal Short-Circuit Forward Current | |
| XZS | (1) | Thaler Corporation has developed a nonlinear compensation network of ther |
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