| Mfg | pack | D/C | Descrpion | ||
| Y00 | (6) | Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz | |||
| Y01 | (6) | TSOP8S | 2007+ | EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting furthe | |
| Y02 | (2) | 00+ | 20000 | TSSOP-8 | The advantages of Current Source Inverters lie in their ease control, abs |
| Y03 | (1) | 2008 | 2) A single check bit error will cause that particular check bit | ||
| Y05 | (3) | FAIRCHLD | TO-220 | 05+ | In addition to real power information, the ADE7756 also provides system |
| Y07 | (2) | MOT | PLCC44 | 03/05+ | Note 2: Without PCB copper enhancements. The maximum power dissipation mu |
| Y08 | (3) | N/A | SANKOSHA | 05+ | Multiformat video decoder supports NTSC-(M, N, 4.43), PAL-(B/D/G/ |
| Y-1 | (6) | SOP-8 | • Complies with USB-IF specifications for USB 2.0, the USB Mass Stor | ||
| Y1- | (10) | WM | Y5P | 05+ | Each Hall effect digital integrated circuit includes a voltage regulator, |
| Y10 | (19) | FAIRCHLD | TO-220 | 05+ | with A10 defining auto precharge) to select one location out of the memor |
| Y11 | (9) | bourns | bourns | dc0442 | HIGH SPEED: tPD =5.8 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTP |
| Y12 | (1) | After the software data protections 3 word command code is given, a wor | |||
| Y13 | (3) | 4000 | ROI | SMD | DRQ DMA Request (Output, active High). This signal is asserted when the c |
| Y14 | (3) | ST | SOT223 | ble 5) is sent first, followed by the Least significant Byte (Table 6). | |
| Y15 | (6) | ST | SOT223 | • JEDEC- and industry-standard x16 timing, functions, pinou | |
| Y16 | (2) | PHI | BGA | 0041+ | Designed for applications that require long battery life while us |
| Y17 | (1) | PMI | 0037+ | Notes: 1. The Standby input must be controlled using an open- co | |
| Y19 | (2) | MIC | DIP-16 | 05+ | The HCPL-7850/7851 is an isolation amplifier that provides accurate, |
| Y1E | (2) | TSOP28 | 38503 | EPSON | In half-duplex mode, all ports support backpressure flow control, to minim |
| Y1F | (3) | SHINDEGEN | SOD-6 | 05+ | Notes: 1. Stresses greater than those listed under absolute maximu |
| Y1M | (1) | The Y1MSB1168M1615BF is 536,870,912 bits synchronous high data ra | |||
| Y1Z | (1) | shindengen | 05+ | FM1233A features a precision temperature-compensated volt- age reference | |
| Y-2 | (2) | Dual 2:1 multiplexer and 1:2 buffer 1C 4 Gbps fully differe | |||
| Y2- | (12) | WM | Y5V | 05+ | The received serial data is internally converted to parallel by th |
| Y2( | (1) | 长电 | SOT-23 | 03+ | Leading edge blanking is also applied to the current limit comparator. |
| Y20 | (20) | PHIL | TSOP | N/A | The DS1543 is a full-function real-time clock/calendar (RTC) with a RTC a |
| Y21 | (10) | COSMO | DIP | 04+ | 6HFXUHG 6LOLFRQ 6HFWRU UHJLRQ ² ZRUGV DFFHVVLEOH WKURXJK D FRPPD |
| Y22 | (23) | NS | . | When applying signals to RECIN (rectifier input) an input series resistor | |
| Y23 | (1) | When VPP is low (VPP = V PPL), the contents of the command latch are fix | |||
| Y24 | (4) | TI | SSOP-20 | The DAC consists of 16 current sources configured to deliver a 10.24 mA | |
| Y25 | (4) | SOP20 | 06+ | The CS8920A requires the minimum number of external components needed f | |
| Y26 | (4) | TI | TSSOP16 | 00+ | The sensor consists of a precision linear Hall IC, which is optimized to |
| Y27 | (2) | TI | 00+ | q NEW DMOS TOPOLOGY: Ultra Low Dropout Voltage: 115mV Typ | |
| Y28 | (2) | Ｓiemens | PQFP100 | 96/97+ | Other operating features include an on/off inhibit, and the ability to st |
| Y29 | (11) | TI | TSSOP-24 | 00+ | The CD4024B types are supplied in 14-lead hermetic dual-in-line ceramic p |
| Y2D | (1) | Keyboard and Mouse Controller (KBC) 8-bit microcontroller, software com | |||
| Y30 | (17) | YAMAHA | SOP | 03/+04+ | • 14-Bit (XRD9814) or 16-Bit (XRD9816) A/D Converter • |
| Y31 | (5) | Built-in H and V drivers (built-in input level conversion circuit, TTL dr | |||
| Y32 | (9) | Notes: (1) ISR-will operate down to no load with reduced specifications. | |||
| Y33 | (13) | Note 1: Absolute Maximum Ratings indicate limits beyond which damage to t | |||
| Y34 | (11) | N/A | SMD | 99 | Hardware data protection measures include a low V CC detector that autom |
| Y35 | (4) | BGA | 99+ | 2.3 Order of precedence. In the event of a conflict between the te | |
| Y36 | (2) | YAMAHA | SMD-20 | 04+ | Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 |
| Y37 | (7) | PHILIPS | O7+ | Maximum ratings are those values beyond which device damage can occur. Ma | |
| Y38 | (1) | ||||
| Y39 | (2) | TI | 01+ | Stresses above those listed under Absolute Maximum Ratings may cause pe | |
| Y-4 | (1) | 10 X 1000 ms, nonCrepetitive 1 square copper pad, FRC4 board FRC4 boar | |||
| Y4- | (2) | KOA | 4x4-47K | 05+ | With its outstanding high-speed performance, the ADS1610 is well-suited |
| Y40 | (2) | PHILIPS | PLCC | 0234+ | The devices also have 96 I/O cells, each of which is directly connected |
| Y41 | (6) | COSMO | SOP-4 | 04+ | The LIS3LV02DQ has a user selectable full scale of 2g, 6g and it is capa |
| Y42 | (4) | FAIRCHILD | 04+ | The Preliminary Information presented herein represents a product in prot | |
| Y43 | (1) | ||||
| Y45 | (1) | Designed to support the requirements of converging networks, the Y45A11101 | |||
| Y49 | (1) | Electrical characteristics are guaranteed over full junction temperature | |||
| Y4A | (1) | Microchip | TO235 | 02+ | The activation energy of the failure mechanism is derived from either inte |
| Y4C | (2) | WALSIN | 0610+ | C 500 ns instruction cycle at 24 MHz operation Superset of the 8051 arc | |
| Y50 | (3) | Power supply sensitivity is a measure of the effect of a power supply ch | |||
| Y51 | (5) | SOP16W | 2007+ | This pin is used to monitor the status of the hook-switch and its combin | |
| Y52 | (4) | The Forward Biased Safe Operating Area curves define the maximum | |||
| Y53 | (4) | The HSMx-L640 is a Chip LED with an integrated lens. The lens concentr | |||
| Y54 | (5) | An example of this situation is a power op amp connected as a current so | |||
| Y55 | (2) | N/A | SI | 04+ | sequences are entered into the device. The command sequences are shown |
| Y59 | (1) | TI | TSSOP16 | The Y5916/Y5916/Y5916 SRAM integrates 2,097,152 x 36/4,194,304 x 18,1,048 | |
| Y5S | (2) | PGND (Bump D3): Power ground pin. Connect directly to the ground plane. | |||
| Y5U | (1) | Operating voltage: +3.3V Programming voltage CVPP=12.5V0.2V CVCC=6.0V0. | |||
| Y5V | (3) | The MM54HCT573 MM74HCT573 octal D-type latches and MM54HCT574 MM74HCT574 | |||
| Y60 | (7) | QFN | A read cycle is initiated by the falling edge of CAS or OE, whichever o | ||
| Y61 | (11) | JAPAN | QFP | 01+ | The photodetector delivers the extracted current to a transimpedance ampli |
| Y62 | (16) | 106 | NEC | 01+/02+ | For the Read and all four Write commands, the data stored within the co |
| Y63 | (12) | TSOP | 9945 | RF MODULATOR OUTPUT The device provides an output, Mod_YC, to drive an | |
| Y64 | (5) | QFN6 | The HT48C10/48C30/48C50/48C70 are 8-bit high performance RISC-like microc | ||
| Y65 | (14) | QFN6 | NEC's Y650ST1S is a GaAs Multi-Chip Module designed for use as input st | ||
| Y66 | (4) | SHARP | TSSOP | 1997 | Each GLB contains 32 macrocells and a fully populated, programmable AND |
| Y67 | (4) | NEC | TQFP | 00+ | Carrier Detect (Active-LOW). These inputs are associated with individual |
| Y69 | (2) | This integrated circuits is manufactured on a CMOS process. It can be dama | |||
| Y70 | (11) | QFN6 | 03+ | With the Hold input held High - Figure 4. As frequencies are inpu | |
| Y71 | (12) | EPCOS | 02+ | BLC210/210HP type are a CCFL driving surface mount inverter transformer w | |
| Y72 | (5) | MICROCHIP | TQFP-64P | 6+ | ✔ Molded JEDEC SO-16 (Wide Body) Package ✔ Weight 0.15 gram |
| Y73 | (2) | QFN6 | HN58X24xxSFPIAG series are two-wire serial interface EEPROM (Electrically | ||
| Y74 | (1) | VIC | DIP | 8911 | Notes: 1. Repetitive Rating : Pulse width limited by maximum junction tem |
| Y75 | (6) | † Not more than one output should be tested at a time, and the dura | |||
| Y76 | (8) | BGA | 2001 | The LM4040 utilizes fuse and zener-zap reverse breakdown voltage trim d | |
| Y77 | (5) | TI | TSSOP8 | 2007+ | The Microchip Technology Inc. 93XX46A/B/C devices are 1K bit low voltag |
| Y78 | (1) | YAMAHA | 0601+ | QFN | The parameters governing address generation are loaded into five 24-bit |
| Y79 | (1) | The ISL6614A drives both the upper and lower gates simultaneously over a | |||
| Y7P | (1) | During Master Reset, LD selects one of two partial flag default offsets ( | |||
| Y80 | (3) | ERICSSON | SOP16S | 06+ | The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporate |
| Y81 | (1) | ALCATEL | ON Semiconductor andare trademarks of Semiconductor Components Industries | ||
| Y82 | (3) | SSI | DIP40 | 2007+ | a. HYB: designator for memory components 25D: DDR-I SDRAMs at Vdd |
| Y83 | (2) | ST | 05++ | SOT23-5 | These devices consist of two independent voltage comparators that are d |
| Y84 | (2) | FEATURES Single or Dual-Supply Operation Excellent Sonic Characteristics | |||
| Y85 | (1) | Note: The HUMMER module itself can sustain continuous voltages of | |||
| Y87 | (4) | NO | 03+ | Power-Good Output 3: Asserted when the following is true: (PWRGD1 = Asse | |
| Y88 | (1) | No part of this document may be copied or reproduced in any form or by an | |||
| Y89 | (2) | 84 | † Stresses beyond those listed under absolute maximum ratings may c | ||
| Y90 | (3) | ALCATEL | The MAX II JTAG and ISP controller internally generate the high programm | ||
| Y91 | (2) | Y | SOP/14 | 02+ | |
| Y92 | (12) | ||||
| Y93 | (1) | Note 8: CPD is defined as the value of the internal equivalent capacitanc | |||
| Y94 | (1) | 02+ | 16 | The Y94AB is an integrated microcircuit incorporating a resistor array | |
| Y97 | (2) | OSCILLATOR The UC3823A,B/3825A,B oscillator is a saw tooth. The rising | |||
| Y99 | (4) | 2008 | 1. In addition to lower output capaci- tance between terminals than ever | ||
| YA- | (5) | An analog to digital (A/D) conversion can be accomplished with ei | |||
| YA/ | (1) | 三洋 | 06-3 | Calibration Cycle Initiate. A minimum 80 input clock cycles logic low f | |
| YA0 | (2) | SOP16 | 06+ | Net List: SYM=POWMOSN .SUBCKT 501N16A 10 20 30 * TERMINALS: D G S * 50 | |
| YA1 | (2) | The UCC5630A is used in multi-mode active termination applications, whe | |||
| YA2 | (6) | TAOperating free-air temperature−55125−4085C NOTE 3: A | |||
| YA3 | (3) | CENTILLIUM | QFP128 | 04+ | Since the MSK 610 is a high voltage amplifier, it is com- monly u |
| YA8 | (13) | FUJI | TO-220 | 45V，30A，肖特基带阻二极管 | Advance/Load Input. Used to advance the on-chip address counter or load a |
| YA9 | (2) | ||||
| YAA | (1) | The MAX3228E/MAX3229E are +2.5V to +5.5V pow- ered EIA/TIA-232 and V.28/V | |||
| YAC | (27) | YAMAHA | DIP | , LTC and LT are registered trademarks of Linear Technology Corpor | |
| YAD | (3) | YAMAHA | 2008 | Delays to tri-state are defined as delay to turn off (VGS < VT) of the | |
| YAE | (4) | The Hynix HYM71V16M655AT6 Series are Dual In-line Memory Modules su | |||
| YAM | (3) | 08+ | 3.3/5.0 VOLT SELECT: 3/5 » high configures internal circuits for 3. | ||
| YAS | (9) | N/A | N/A | N/A | The feedback path of the PLL is internal. The PLL adjusts the VCO |
| YAT | (5) | SANYO | 06+ | 500 | The FM803 is a supervisory device designed to monitor power supply or o |
| YAV | (4) | TLE 4729 G is a bipolar, monolithic IC for driving bipolar stepper motors | |||
| YAW | (9) | N/A | N/A | N/A | Absolute Maximum Ratings are those values beyond which damage to the devi |
| YAY | (1) | The PLL602-03 is a low cost, high performance and low phase noise XO, pr | |||
| YAZ | (1) | N/A | DIP8 | 06+ | The ML6102 is a group of high-precision and low-power voltage detectors. |
| YB0 | (2) | 8-Bit Resolution 25MHz Conversion Rate 60MHz 3dB Analog Input Bandwidt | |||
| YB1 | (14) | SZHG | SOP | 04+ | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V |
| YB2 | (2) | YB | The FAN4174 is a single, ultra-low cost, voltage feedback amplifier | ||
| YB3 | (3) | FUJI | TO220F | All ESD diodes are designed to safely handle the high current spikes sp | |
| YB6 | (2) | 2000 | DIP4 | During power-up, the output is momentarily preset to midscale befo | |
| YB8 | (1) | The dual-enable configuration gives the bus transceiver the capability to | |||
| YBA | (1) | PANASONIC | The dual ADC core features a multistage differential pipelined architect | ||
| YBG | (2) | N/A | 1206LED | Œ120 V AC resistive load (CHB type) 30 V DC resistive load (C | |
| YC- | (1) | Test data input. One of four terminals required by IEEE Standard 1149.1-1 | |||
| YC0 | (9) | NEC | BGA | 2000 | Housed in SOIC−8 or PDIP−8 package, the NCP1201 enhanc |
| YC1 | (126) | N/A | To allow for dc coupling to ADCs, its unique output common-mode control | ||
| YC2 | (6) | N/A | Fifth Generation HEXFETs from International Rectifier utilize advanced | ||
| YC3 | (10) | The YC324-JK-07100 is versatile in its applications, including uses in | |||
| YC5 | (3) | N/A | The W83877TF provides two high-speed serial communication ports (UARTs), | ||
| YC7 | (2) | The LM1881 also generates a default vertical sync pulse when the vertic | |||
| YC8 | (1) | The initialization and resynchronization methods described in their res | |||
| YC9 | (1) | N/A | N/A | Supersedes the Zoran ZR36057. Glueless interface to PCI bus (PCI spec. | |
| YCA | (1) | Makes DRAM Interface and refresh tasks appear virtu- ally transparent to | |||
| YCC | (3) | ETRONIC | 1206 | The bar antenna is a very critical device of the complete clock receiver | |
| YCE | (1) | N/A | • T1 Digital Cross-Connects (DSX-1) • ISDN Primary Rate Interf | ||
| YCF | (1) | CY | Q | 00+ | Low operating frequencies can become a concern if they are in the audibl |
| YCK | (23) | murata | murata | dc71+ | Interrupt Request: Is used as a general purpose interrupt. It is sampled |
| YCL | (3) | YCL | 488 | 0126+ | Note 1: The minimum operating voltage is 2.65V; however, the device is gua |
| YCM | (5) | Hitac his ser ia l EEP RO M ar e author iz ed for using consume r applica | |||
| YCN | (12) | 0603X5(10P8R) | The output of the VCOD is the full speed output frequency seen on the CLK | ||
| YCP | (2) | 75 | FAROUDJA | 97+ | Operating temperature range is as follows: 0C to +50C. Fre |
| YCR | (1) | 500 | 94+ | Single Down/Up Count Control Line Look-Ahead Circuitry Enhances Speed of | |
| YCS | (1) | ST | SOP20 | Five product terms from the programmable AND array are allocated to eac | |
| YCT | (1) | YAGEO | N/A | • HFBR-5701L: Dual specified 1.25 GBd Ethernet (1000BASE-SX) | |
| YD- | (6) | The transceiver can also replace parallel data transmission architectures | |||
| YD0 | (2) | CHEECHEN | 06+ | The crystal or clock frequency chosen must be twice the required process | |
| YD1 | (4) | YD | SOP28 | The CPU features two sets of functional units. Each set contains four uni | |
| YD2 | (15) | AD | 8PIN-CDIP | 07+ | 1) CPD is defined as the value of the ICs internal equivalent capacitance |
| YD3 | (7) | YD | SOP14 | The information contained herein is presented only as a guide for t | |
| YD4 | (3) | N/A | DIP | 01+ | Input Data Mask: DM is an input mask signal for write data. Input data is |
| YD5 | (4) | 07+/08+ | Support for one Fibre Channel port Support for 1- and 2-Gb serial inter | ||
| YD6 | (8) | DIP8 | 07+ | The output voltage accuracy in the PWM mode is well within 3% of | |
| YD7 | (6) | DIP8 | 07+ | • 9.5 MSEC average seek time • 5,400 rpm Spindle Speed • | |
| YD8 | (6) | YD | DIP-14 | 2003 | Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATING |
| YDA | (16) | 22 | YAMAHA | O2+ | The HYM72V64636H(L)T8 Series are 64Mx64bits Synchronous DRAM Modules. The |
| YDC | (15) | 02+ | A buffered output-enable (OE) input can be used to place the eight output | ||
| YDM | (2) | N/A | Like the PEEL18CV8, the YDM-1005 is a logical superset of the industry st | ||
| YDN | (2) | The IRU3027 controller IC is specifically designed to meet VRM 9.0 specif | |||
| YDR | (1) | sgs | sgs | dc80+ | • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY fmax = 280MHz* Ma |
| YDS | (27) | N/A | The HC4066 and CD74HCT4066 contain four independent digitally controlle | ||
| YDU | (1) | 94 | The Schottky Powermite employs the Schottky Barrier principle wit | ||
| YDW | (1) | YEONHO | The MAX1393/MAX1396 micropower, serial-output, 12- bit, analog-to-digital | ||
| YE0 | (3) | MOT | DIP-28 | 03+/04+ | Notes: 6. Parameters are guaranteed by design and characterization |
| YE1 | (3) | Figure 1 shows a typical soldering profile for the D2 and D3 Packages whe | |||
| YEA | (15) | Panasonic | 2003 | Signal input pin. A internal matching circuit, configured with resisto | |
| YED | (5) | MOT | 04+ | ParameterUnitsValue Lamp Type2/32T82/40T12 Input Power[W]6580 I | |
| YEL | (1) | MOT | 22 | This is a four-state pin. DF/DCS = VA, output data format is offset bin | |
| YEM | (1) | DIP18 | 9633+ | This specification describes the Bt8110 and Bt8110B multichannel ADPCM pro | |
| YER | (1) | Notes: 1. Load and Line Regulation are specified at a constant junction | |||
| YES | (1) | All inputs, outputs, and clock signals on the TMS551xx devices are compat | |||
| YF- | (1) | On a single 5V supply, the LT1990 has an adjustable 85V input range, 70dB | |||
| YF0 | (2) | Information furnished by Calogic is believed to be accurate and reliable. | |||
| YF1 | (2) | IC-VF | SOP16 | The Hynix HYM7V75AS1601B N-Series are 16Mx72bits ECC Synchronous DRAM Modu | |
| YF2 | (4) | Control ST-BUS In is a TTL-compatible digital input used to control the fu | |||
| YF3 | (1) | 5 | SOP | While P0.0 anbd P0.1 differ from standard TTL characteristics, they are c | |
| YF4 | (2) | WALL | stock | In addition to the data sheet changes made above due to product enhanceme | |
| YF7 | (1) | SOP | 505 | When 16/68# pin is at logic 1, it selects Intel bus interface and this i | |
| YF9 | (2) | OPTI-LOOP compensation allows the transient response to be optimized over | |||
| YFA | (1) | Note: 5. This input level is calculated from the input power delivered t | |||
| YFB | (1) | N/A | 05+ | C Single Cycle Reprogram (Erase and Program) C 4096 Pages | |
| YFD | (8) | YOUTH | Specified Performance High Speed Mode: SCL = 3.4MHz | ||
| YFE | (1) | Notes: 1 Monitoring time is the time from the last pulse (negative | |||
| YFR | (1) | • Message bit rates up to 1 Mbps • Conforms to CAN 2.0B ACT | |||
| YFS | (4) | SOP | 04+ | For the system/MAC interface, seamless support is provided for the Motor | |
| YFT | (2) | 06+ | Note 1: Absolute Maximum Ratings are those values beyond which the life | ||
| YFW | (11) | SAM | BGA | 5 | Extended Data Out (EDO) Operation CAS-Before-RAS ( CBR) Refresh High-Imp |
| YFX | (1) | ECOS1JA122AA ECOS1JA152AA ECOS1JA182AA ECOS1JA681BL ECOS1JA681BA ECOS | |||
| YG- | (1) | Forward-Current Transfer Ratio IC = 1.0 Adc, VCE = 3.0 Vdc | |||
| YG1 | (4) | ROHM | 06+ | The EP7311 includes two 16550-type UARTs for RS-232 serial communication | |
| YG2 | (15) | ROHM | 06+ | The software protection is a register based read and write protection i | |
| YG3 | (5) | FUJI | TO220F | This document is a general product description and is subject to change wi | |
| YG4 | (2) | MIC | QFN-16 | 06+ | In contrast to the BTS 7710 G, which consists of the same chips in an P-D |
| YG5 | (2) | YAHAMA | 01+ | 500 | Special handling is required for Flash Memory products in TFBGA packages. |
| YG6 | (2) | fuj | 02+ | 1.125 (28.56mm) PCB Height 168-Pin Registered DIMM with Double Sided ECC | |
| YG8 | (81) | FUJI | TO-220 | 08+ | • Generation 4 IGBTs offer highest efficiencies available |
| YG9 | (28) | FUJI | TO-220 | 05+ | EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output |
| YGB | (1) | YAMAHA | QFP/160 | 07+ | A buffered output-enable (OE) input can be used to place the eight output |
| YGC | (1) | DATA (Pin 8): Input/Output. Microcontroller side data I/O pin. The DATA p | |||
| YGF | (1) | YAMAHA | QFP | 2000 | Input HIGH Voltage (Input pins) Input HIGH Voltage (I/O pins) Input LOW |
| YGH | (4) | LG INNOTEK | 05+ | Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung | |
| YGK | (1) | SMD | 9822 | ‡ All typical values are at VCC = 5 V, TA = 25C. For I/O ports, | |
| YGR | (2) | HIT | 06-07+ | Like almost all IC power regulators, the LX8385/85A/85B regulators are e | |
| YGS | (1) | The inductor and varactor elements of the tank are inte- grated on-chip, | |||
| YGT | (9) | HITACHI | O7+ | ||
| YGU | (1) | The SCAN18541T is a high speed, low-power line driver featuring separat | |||
| YGV | (23) | Because the P87LPC768 combines an embedded ADC and PWM, it is especially | |||
| YH- | (3) | SIPEX(stock) | SOP-1603(specialty) | 25+(advatage series) | MAX 7000A devices use CMOS EEPROM cells to implement logic functions. Th |
| YH0 | (1) | DIP-8 | Power Supply Input. These parts can be operated from 1.65 V to 2.75 V; V | ||
| YH1 | (2) | The receive part is designed for a double conversion architecture. The in | |||
| YH2 | (4) | DNSN | PLCC-84 | To save pins without loosing speed, the TV-SAM is addressed serially usin | |
| YH4 | (1) | 715 | CONEXANT | 01+ | NOTE 1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle r |
| YH7 | (1) | Description Reference clock select. When LOW, selects REF0 and REF0/VREF | |||
| YH8 | (1) | sharp | sharp | dc98+ | There are two popular conventions for establishing the rela- tive phasin |
| YH9 | (5) | HARRIS | QFP | 2. Intersil Pb-free plus anneal products employ special Pb-free material | |
| YHA | (2) | • Photo detector and preamplifier in one package • Internal | |||
| YHF | (1) | 3.3V Operation with 5V Tolerant Buffers ACPI 1.0b/2.0 and PC99a/PC2001 Co | |||
| YHG | (1) | PANASONIC | . | 240 | The products may contain design defects or errors known as errata, which |
| YHI | (1) | ROHM | The PWM signal is the control input for the driver. The PWM signal can | ||
| YHM | (2) | M/A-COM | (LX)high-frequency | Output Capacitors: The PT6700 series requires a minimum ouput capacitance | |
| YHQ | (1) | TACHIB | TQFP7*7 | 03+ | Typical specifications represent average readings at 25C and VDD = |
| YHU | (1) | LED PULSE The 9Cvolt battery level is checked every 40 seconds du | |||
| YI- | (1) | DIP-8 | Typical system performance parameters for the receiver are 93 dB gain, 7 | ||
| YIA | (1) | QFP | 01+ | When VCC is between 0 and 1.2 V, the device is in the high-impedance stat | |
| YIE | (1) | EPSON | SSOP28 | 03+/04+ | Notes: 1. All byte outputs are active in read cycles regardless of the s |
| YIK | (1) | Like all members of the FLASH370i family, the CY7C375i is rich in I/O res | |||
| YIN | (1) | 766 | ATNEL | O2 | Transceiver I/O Truth Table The outputs (LED and RXD) are controlled b |
| YIS | (5) | sgs | sgs | dc70+ | Since the ADR512 characteristics resemble those of a Zener diode, the ca |
| YIZ | (1) | QFN | 06+ | Before valid data exchanges between the serializer and deserializer can r | |
| YJ- | (1) | YAMAHA | 95+ | n Targeted at WXGA (1280x768) and HDTV (1366x768) applications fo | |
| YJ0 | (1) | In the receive signal path, the RF input is converted to low IF In-phase | |||
| YJ1 | (3) | The M54/74HCT245, HCT640 and HCT643 utilise silicon gate C2MOS technolo | |||
| YJ2 | (1) | ||||
| YJ3 | (1) | TI | 200 | 03+ | Input Data Mask: DM(0~3) is an input mask signal for write data. Input dat |
| YJR | (1) | Reset Output. RESET is an active LOW, open drain output which goes active | |||
| YK- | (2) | 红宝石 | 6.3＊11 | 05+ | The DS1809 Dallastat is a digitally controlled, nonvolatile potentiometer. |
| YK0 | (2) | ST | 06+ | Power Supply X+ Position Input Y+ Position Input XC Position Input | |
| YK2 | (1) | Hynix HYMD264726A(L)8-M/K/H/L series is unbuffered 184-pin double data rat | |||
| YK5 | (7) | avx | avx | dc00 | It contains a Single-Ended (SE) power stage, drive logic, protection cont |
| YK8 | (1) | ||||
| YKB | (2) | Table of contents PPAP Checklist 1. Design Records 2. Engineering Chang | |||
| YKC | (26) | SIEMENS | 06+ | The ADM2486 driver has an active-high enable feature. The driver differe | |
| YKE | (1) | A MOSFET pass element delivers high output current with an input- | |||
| YKF | (4) | ||||
| YKL | (1) | The XRT75VL00D incorporates an advanced crystal- less jitter attenuator | |||
| YKS | (1) | KYOCERA | 03+ | The device features simultaneous read/write op- eration, which allows t | |
| YL2 | (11) | TI | 260 | 01+ | Each of the macrocells on the CY7C373i has a separate I/O pin associated |
| YL3 | (2) | Acknowledge is a software convention used to provide a positive handsha | |||
| YL4 | (1) | DIP | 98 | n Fourteen multi-source vectored interrupts servicing External i | |
| YL9 | (3) | N/A | 06+ | 850 | The WEL bit controls the access to the CCR and mem- ory array during a |
| YLA | (1) | The device also includes a 1 volt regulator capable of sourcing u | |||
| YLB | (1) | sie | sie | dc89 | The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/ 016AV/017AV are l |
| YLP | (1) | The device is compatible with the JEDEC single power-supply Flash comma | |||
| YM- | (5) | CAUTION: Stresses above those listed in Absolute Maximum Ratings may caus | |||
| YM0 | (2) | YAMAHA | DIP | Screen tested 100% on each device at +25C, +125C and -55C temperat | |
| YM1 | (8) | YAMAHA | In the Si9167, the error amplifier output is compared with the 0.5-V pea | ||
| YM2 | (63) | YAMAHA | . | 2 | • JEDEC standard 3.3V power supply • LVTTL compatible with mu |
| YM3 | (107) | YAMAHA | 9511 | NOTES: 1.Dimensions are in inches. 2.Metric equivalents are given for | |
| YM4 | (7) | YAMAHA | Stresses beyond those listed under "absolute maximum ratings" m | ||
| YM5 | (3) | YAMAHA | SUMMARY DESCRIPTION The M29W400B is a 4 Mbit (512Kb x8 or 256Kb x16) no | ||
| YM6 | (33) | YM | When Vcc is between 0 to 1.5V during power up or power down, the outputs | ||
| YM7 | (32) | YAMAHA | 2000+ | QFP-48 | Retires as many as three instructions per clock cycle Separate on-chip L |
| YM9 | (2) | N/A | N/A | N/A | (1) S/N can be improved for common mode noise on internal and external sig |
| YMA | (2) | This device contains circuits to protect its inputs and outputs against d | |||
| YMB | (1) | star micronics | star micronics | dc06+ | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V |
| YMC | (3) | SOP | YAMAHA | Pin and Software Compatibility with Standard 80C51 Products and 80C51Fx/R | |
| YMD | (1) | Common Mode Voltage. The voltage output at this pin is required to be t | |||
| YME | (4) | QFP | N/A | The YME289B is organized as four 4-bit bus switches with separate output- | |
| YMF | (87) | YAMAHA | QFP100 | FEATURES • Two 10-bit Nonvolatile DACs − INL 1 | |
| YMO | (1) | YAMAHA | DIP | s Fully complies with Universal Serial Bus Specification Rev. 2.0 | |
| YMS | (1) | Line Drivers are available for the HEDS-55xx/56xx series and the HEDS-90 | |||
| YMU | (76) | N/A | 0810+ | Hitachi Europe GmbH Electronic components Group Dornacher Straß | |
| YMW | (6) | YEONHO | 2004 | ||
| YMY | (1) | YAMAHA | O7+ | (1) Offset error is the deviation of the average code from mid-code for a | |
| YMZ | (30) | YAMAHA | 06+ | 2000 | • High current sink/source 25 mA/25 mA • Three external int |
| YN0 | (4) | N/A | 99+ | Notes: 12. Minimum limits are specified but not tested on Propagat | |
| YN1 | (2) | 94 | Features International standard packages JEDEC TO-247 AD and TO-2 | ||
| YN2 | (1) | N/A | 06+ | 500 | |
| YNL | (2) | Notes: (1) Thermal resistance from junction to ambient with units mounte | |||
| YNM | (1) | 1. Laser trimming of both initial accuracy and temperature coeffi | |||
| YNR | (1) | SANYO | QFP-80 | 04+ | NOTES: 1. Stresses beyond those listed may cause permanent damage to the |
| YNS | (3) | 151 DQ42 152 153 DQ43 154 155 VDD 156 157 VDD 158 159 VSS 160 161 VSS | |||
| YO2 | (1) | SAM | QFP | 95+ | Both devices operate from a single +3.0V to +5.5V sup- ply and require no |
| YO4 | (1) | In the 10-bit mode the 8b/10b Codec is disabled, and the externally encod | |||
| YO6 | (1) | 2001 | which includes the control and status registers of the on-chip peripher | ||
| YO7 | (1) | 2001 | TXCLK is an internally derived 1200 or 2400 Hz signal in internal mode an | ||
| YOP | (1) | • Four Crystal modes, up to 40 MHz • 4x Phase Lock Loop (PL | |||
| YOU | (1) | CPU_STP# is an input to the clock generator. CPU_STP# is asserted asynch | |||
| Y-P | (1) | (600R) | The SD1010A implements four advanced display technologies: 1. Advanced mo | ||
| YP- | (5) | Within each logic block there are 16 macrocells. Macrocells can either | |||
| YP0 | (2) | 94 | Low Side Driver Output. This pin must be connected to the gate of the hal | ||
| YP2 | (1) | The Receiver utilizes a discrete silicon PIN photo-diode with an integ | |||
| YP9 | (1) | Burst mode operation Auto & self refresh capability (8 | |||
| YPA | (1) | NOTES: 1. The device may be operated outside recommended frequency ranges | |||
| YPB | (1) | The MC33399 includes the 30kohm LIN pull-up so this does not need to be | |||
| YPC | (1) | In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to | |||
| YPD | (1) | The recommended dose of ultraviolet light for erasure is a wavelength of | |||
| YPE | (1) | IN, FB, SHDN to AGND OUT to AGND, LX to PGND AGND to PGND OUT Short Cir | |||
| YPM | (1) | Cavity-free glass-passivated junction Ideal for automated placement Ul | |||
| YPP | (6) | The MAX2602 includes a high-performance silicon bipolar RF power transist | |||
| YPY | (2) | 90% Efficiency at 20W Frequency to 600kHz 30W output at 22Vin 2.4V to 2 | |||
| YQ4 | (6) | Designers must not rely on the absence or characteristics of any features | |||
| YQP | (3) | Analog Ground. Receive Input. Analog receive input. This pin is internall | |||
| YR0 | (1) | FDDI is a Dual Token Ring standard developed in the U.S. by the Accredit | |||
| YR1 | (1) | vitramon | vitramon | dc82+ | The detector output voltage (Pdet) range can be adjusted by the value of |
| YR2 | (11) | NANA | VCCL, VCCR, VLC0L, VLC0R, VLC1L, VLC1R, VLC4L, VLC4R, VLC5L and VLC5R Re | ||
| YR4 | (6) | Input MUX control input, hold high to select LHP IN or RHP IN (5, 20), ho | |||
| YRB | (1) | N/A | 05+ | NanoStar and NanoFree Packages Supports 5-V VCC Operation | |
| YRC | (4) | a.b. | a.b. | dc80+ | The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve hig |
| YRN | (5) | sfernice | sfernice | dc80+ | 1Cwire communication using the DS1481 is impossible in transparent mode |
| YRW | (16) | dale | dale | dc71+ | DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . - |
| YS- | (16) | Pulse width and repetition rate should be such that the device junction t | |||
| YS1 | (23) | 08+ | The HY29F800s sector erase architecture allows any number of array sect | ||
| YS2 | (4) | YAMANA | . | Designed for N- CDMA base station applications with frequencies fr | |
| YS3 | (1) | Reader Response: To improve the quality of our publications, we welcome y | |||
| YS5 | (9) | N/A | 07+ | Module | Vishay Siliconix maintains worldwide manufacturing capability. Products ma |
| YS7 | (1) | Minimum time between read command (i.e., a write to communication regist | |||
| YS9 | (2) | This chip, when properly assembled, displays characteristics similar to t | |||
| YSB | (1) | TI | QFP | ||
| YSC | (6) | N/A | The LTE-3271T/LTE-3371T/LTE-3217TL/LTE-3371TL are high intensity Galliu | ||
| YSD | (5) | YAMAHA | SMD | 4 | The Fairchild Switch FSTU3125 provides four high-speed CMOS TTL-compatib |
| YSF | (4) | yam | yam | dc98 | Output-enable (OE) and direction-control (DIR) inputs are provided to con |
| YSH | (2) | We Listen to Your Comments Any information within this document that you | |||
| YSK | (1) | The PACSZ1284 provides a complete parallel port ter- mination solution. | |||
| YSO | (1) | INSPECTED | SOP/8 | The AD9748 is a 8-bit resolution, wideband, third generation member of t | |
| YSP | (3) | Notes: Stresses greater than those listed under MAXIMUM RATINGS may cau | |||
| YSS | (66) | Gated PWM operation The internal circuitry of the YSS247-E is turned off | |||
| YST | (3) | N/A | Intersil semiconductor products are sold by description only. Intersil Co | ||
| YSW | (1) | 0506+ | Please retain the carton and packing materials, as this is the best protec | ||
| YT- | (3) | TOKIN | Module | N/A | NOTES 1Sample tested during initial release and after any redesign or pr |
| YT1 | (1) | The Connect Memory data is received via the Microprocessor Interface at D0 | |||
| YT2 | (2) | YOUTHTECH | 04+ | In addition, each material offers a specific reliability rating. It is | |
| YT3 | (2) | TDK | † Stresses beyond those listed under absolute maximum ratings may c | ||
| YT4 | (1) | The PRECHARGE command is used to deactivate the open row in a particula | |||
| YT5 | (1) | N/A | N/A | This N-Channel power MOSFET is manufactured using the inn | |
| YT6 | (1) | Motorola, the Motorola logo and VMEexec are registered trademarks of Moto | |||
| YT9 | (1) | ||||
| YTA | (10) | TOS | 03+ | To-220 | A 2 to 1 multiplexer is provided on each filter channel. The triple |
| YTB | (2) | MOT | ZIP | 07+ | • IXYS advanced low gate charge process • Internatio |
| YTC | (3) | YT? | QFN? | 0531+? | Diaensionare in inches.a IMric eguivaleota are given for g |
| YTD | (22) | The LM129 is packaged in a 2-lead TO-46 package and is rated for operat | |||
| YTE | (7) | 93 | Features include an internal programmable slope compensation circuit, p | ||
| YTF | (104) | MOTOROLA | 03+ | To achieve contrast control, pin 1 is shorted to pin 2 and pin 3 | |
| YTK | (3) | The feedback voltage pin is the non-inverting input to the PWM comparator. | |||
| YTL | (2) | XILINX | QFP | N/A | External Access enable: EA must be externally held low to enable the de |
| YTM | (7) | HIT | PLCC68 | 03/+04+ | A novel gate-to-drain feedback capacitance network is used to model the g |
| YTN | (1) | During the pre-equalizing, vertical sync and post equalizing periods, com | |||
| YTQ | (6) | The YTQ-116-03-F-Q is a monolithic Bidirectional Parallel port designed | |||
| YTR | (1) | ∗ This is a stress rating only and functional operation of the devi | |||
| YTS | (9) | TOSHIBA | 4000 | Complete Sensorless control IC for Permanent Magnet AC motors No phase | |
| YTT | (3) | MOT | ZIP | 07+ | Broadcom®, the pulse logo, and Connecting everything®, and QAMLink |
| YTW | (3) | Note 10: This output data pulse position works for TTL inputs except the | |||
| YTY | (1) | 0093+ | Sirenza Microdevices SBB-5089 is a high performance InGaP HBT MMIC amplif | ||
| YTZ | (1) | YAMAHA | 06+ | One of the industry's first ultra high-speed, 8-bit data converters with | |
| YU4 | (1) | The UCC39421 family of synchronous PWM controllers is optimized to oper | |||
| YUA | (2) | 98 | The Intersil ISL43140CISL43142 devices are CMOS, precision, quad analog | ||
| YUE | (1) | 4 | 2004/ | The built-in analog VCO is composed of a ring oscillator portion for osci | |
| YUF | (1) | 00+ | SSOP | protection, and an input under- voltage lockout. In addition, both out | |
| YUK | (1) | NSC | 2008 | The RC2211 does not have a separate VCO output terminal. Instead, the VC | |
| YUM | (3) | AGERE | O7+ | The manual reset input (MR) allows other reset sources, such as a manual | |
| YUP | (2) | TI | SSOP-56 | 02+ | Stresses above the ratings listed below can cause permanent damage to the |
| YV0 | (1) | AL,BL,CL - Are the lowside logic level digital inputs. These three input | |||
| YV2 | (2) | YAMAHA | QFP | 07+ | Note 1: LXSU has internal clamp diodes to PVSU and PGSU, LXM has internal |
| YVE | (2) | 4 | 2004/ | READ clock input with pull-high resistor. Data in the RAM of the HT1626 ar | |
| YVL | (3) | YAMAHA | The following briefly describes a procedure for evaluating the high effic | ||
| YVZ | (4) | YAMAHA | QFP-64 | 9518 | D0 - D4 (DAC Digital Input Control Codes): These are the DAC digital inp |
| YW- | (1) | UNION | DIP | 97+ | ROM data by two table read instructions: ²TABRDC² and ²TAB |
| YW1 | (8) | COSEL | This single-bit noninverting bus transceiver uses two separate configurab | ||
| YW3 | (2) | N/A | SOP8 | The capacitance (Ciss) is read from the capacitance curve at a voltage c | |
| YW4 | (1) | The HT812L0 is a voice and melody synthesizer LSI with 2.8-second voice c | |||
| YW5 | (3) | Module | N/A | Offerings include ball grid array (BGA) packages with 0.80 mm, 1.00 mm, | |
| YW6 | (1) | 70 | O6 | External Headphone Amplifier Power Switch Control Pin 1 H: Normal Opera | |
| YW8 | (7) | INTEL | 06+ | 1100 | • For indirect jumps and calls that use a 16-bit DAG address |
| YWC | (1) | VIN = 2V VIN = 2V VFBx = 1.4V, VLFB > VBRT C 0.1V VFBx = 1.4V, VLF | |||
| YWF | (1) | QFP | Isolated Power Supply: Dual regulated supplies, completely isolated from | ||
| YWL | (3) | This document contains information on a product under development at Adva | |||
| YX1 | (3) | AP | 032 | The discriminator allows the connection of a ceramic resonator or LC tan | |
| YX2 | (1) | YX | 06+ | 1000 | n 2-wire, SMBus 2.0 compliant, serial digital interface n 8-bit Ó |
| YX3 | (1) | DIP-8 | 13. LOCAL/DISTANT SELECTOR (L/D) Press this button to select local | ||
| YX4 | (1) | The B-port has an output enable, OEB0, which affects all seven drivers. | |||
| YX9 | (2) | 9622 | C Single Cycle Reprogram (Erase and Program) C 4096 Pages | ||
| YXD | (1) | Remote On/Off: An open-collector (open-drain) positive logic input that i | |||
| YXF | (1) | The HA-460 Series of quartz crystal oscillators are resistance welded in | |||
| YY0 | (4) | NEC | 03+ | QFN | The addition of a bias circuit in conjunction with this process results i |
| YY1 | (1) | As +5V is used as the reference voltage to generate the loop current, any | |||
| YY2 | (1) | * Specifications will vary with foreign standards certificati | |||
| YY3 | (2) | STM | 1728 | PRS initializes the read and write pointers to zero and sets the output re | |
| YY5 | (1) | ON | 07+ | The low-voltage serial-peripheral interface (SPI™) DS1390/DS1391 an | |
| YY8 | (2) | a. DC characteristics are design targets and pending characterization. b | |||
| YY9 | (1) | The oscillator output is a triangular wave with a minimum value of approx | |||
| YYA | (4) | ROHM | 06+ | 1600 | FM1233A features a precision temperature-compensated volt- age reference |
| YYC | (8) | NEC | LPP | 03+ | As shown in Equation 2 and Equation 3, large capacitor values for the in |
| YYD | (5) | 500 | YAMAHA | 01+ | Not 100% tested. CB = total capacitance of one bus line in pF. As a tran |
| YYJ | (1) | MOT | ZIP | 07+ | The device is entirely command set compatible with the JEDEC single-powe |
| YYN | (1) | MOT | TO | 07+ | The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36 and 524,288 x 18 SRA |
| YYQ | (1) | 93 | The IC is designed specifically to work with appliances, ATM machines, se | ||
| YYS | (2) | 单排P15 | 04+ | The UCC3813-0/-1/-2/-3/-4/-5 oscillator generates a sawtooth waveform on | |
| YYW | (1) | 93 | Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V | ||
| YZ4 | (1) | tpZL15nsEnable time, high-impedance-to-low-level output (1) All ty | |||
| YZK | (1) | NEC | DIP | 2004 | DESCRIPTION The L7800 series of three-terminal positive regulators is |
About Seekchip- Services - Comments - Contact us - Links - Map
© 2008 China Electronics Market,License 浙ICP备10014259号